Datasheet

MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
16
POST OFFICE BOX 655303  DALLAS, TEXAS 75265
memory organization
MSP430F47126/
MSP430F47127
MSP430F47163/
MSP430F47166/
MSP430F47167
MSP430F47173/
MSP430F47176/
MSP430F47177
MSP430F47183/
MSP430F47186/
MSP430F47187
MSP430F47193/
MSP430F47196/
MSP430F47197
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
56KB
0FFFFh -- 0FFC0h
0FFFFh--002100h
92KB
0FFFFh -- 0FFC0h
018FFFh--
002100h
92KB
0FFFFh -- 0FFC0h
019FFFh--
003100h
116KB
0FFFFh -- 0FFC0h
01FFFFh--
003100h
120KB
0FFFFh -- 0FFC0h
01FFFFh--
002100h
RAM (Total) Size 4KB
020FFh--01100h
4KB
020FFh--01100h
8KB
030FFh--01100h
8KB
030FFh--01100h
4KB
020FFh--01100h
Extended Size 2KB
020FFh--01900h
2KB
020FFh--01900h
6KB
030FFh--01900h
6KB
030FFh--01900h
2KB
020FFh--01900h
Mirrored Size 2KB
018FFh--01100h
2KB
018FFh--01100h
2KB
018FFh--01100h
2KB
018FFh--01100h
2KB
018FFh--01100h
Information memory Size
Flash
256 Byte
010FFh--01000h
256 Byte
010FFh--01000h
256 Byte
010FFh--01000h
256 Byte
010FFh--01000h
256 Byte
010FFh--01000h
Boot memory Size
ROM
1KB
0FFFh--0C00h
1KB
0FFFh--0C00h
1KB
0FFFh -- 0C00h
1KB
0FFFh--0C00h
1KB
0FFFh--0C00h
RAM
(mirrored at
018FFh -- 01100h)
Size 2KB
09FFh--0200h
2KB
09FFh--0200h
2KB
09FFh--0200h
2KB
09FFh--0200h
2KB
09FFh--0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh--0100h
0FFh--010h
0Fh--00h
01FFh--0100h
0FFh--010h
0Fh--00h
01FFh--0100h
0FFh--010h
0Fh--00h
01FFh--0100h
0FFh--010h
0Fh--00h
01FFh--0100h
0FFh--010h
0Fh--00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Memory Programming User’s
Guide, literature number SLAU265.
BSL FUNCTION PZ PACKAGE PINS
Data Transmit 91 - P1.0
Data Receive 90 - P 1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A might contain calibration data. After reset segment A is protected against programming or
erasing. It can be unlocked but care should be taken not to erase this segment if the calibration data is
required.
D Flash content integrity check with marginal read modes.