Datasheet

MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
13
POST OFFICE BOX 655303  DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (at 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU enters LPM4 after power-up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out-of-Range (see Note 4)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 31, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 30
Timer_B3 TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 29
Timer_B3
TBCCR1 to TBCCR2 CCIFGs
TBIFG (see Notes 1 and 2)
Maskable 0FFF8h 28
Comparator_A CAIFG Maskable 0FFF6h 27
Watchdog Timer WDTIFG Maskable 0FFF4h 26
USCI_A0/B0 Receive
USCI_B0 I2C Status
UCA0RXIFG, UCB0RXIFG
(see Notes 1 and 5)
Maskable 0FFF2h 25
USCI_A0/B0 Transmit
USCI_B0 I2C Receive/Transmit
UCA0TXIFG, UCB0TXIFG
(see Notes 1 and 6)
Maskable 0FFF0h 24
SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0FFEEh 23
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 22
Timer_A3
TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2)
Maskable 0FFEAh 21
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 20
USCI_A1/B1 Receive
USCI_B1 I2C Status
UCA1RXIFG, UCB1RXIFG
(see Notes 1 and 5)
Maskable 0FFE6h 19
USCI_A1/B1 Transmit
USCI_B1 I2C Receive/Transmit
UCA1TXIFG, UCB1TXIFG
(see Notes 1 and 6)
Maskable 0FFE4h 18
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 17
Basic Timer1/RTC BTIFG Maskable 0FFE0h 16
DMA DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 1 and 2)
Maskable 0FFDEh 15
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0FFDCh to 14 to
Reserved Reserved (see Note 8)
0FFC0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges.
5. USCI_B in SPI mode: UCBxRXIFG. USCI_B in I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG
6. USCI_B in SPI mode: UCBxTXIFG. USCI_B in I2C mode: UCBxRXIFG, UCBxTXIFG
7. The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY).
A 0x0AA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.