Datasheet

MSP430F471x3, MSP430F471x6, MSP430F471x7
MIXED SIGNAL MICROCONTROLLER
SLAS626C -- OCTOBER 2008 -- REVISED MARCH 2011
10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL I/O DESCRIPTION
NAME NO. I/O DESCRIPTION
P3.0/
UCB0STE/UCA0CLK
75 I/O
General-purpose digital I/O /
USCI_B0 slave transmit enable / USCI_A0 clock input/output
P2.7/CA1 76 I/O General-purpose digital I/O / Comparator_A input
P2.6/CA0 77 I/O General-purpose digital I/O / Comparator_A input
P2.5/
UCA0RXD/UCA0SOMI
78 I/O
General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave out/master in in SPI
mode
P2.4/
UCA0TXD/UCA0SIMO
79 I/O
General-purpose digital I/O / USCI_A0 transmit data output in UART mode, slave in/master out in
SPI mode
P2.3/
UCB1CLK/UCA1STE
80 I/O
General-purpose digital I/O /
USCI_B1 clock input/output / USCI_A1 slave transmit enable
P2.2/
UCB1SOMI/UCB1SCL
81 I/O
General-purpose digital I/O /
USCI_B1 slave out/master in in SPI mode, SCL I
2
C clock in I
2
C mode
P2.1/
UCB1SIMO/UCB1SDA
82 I/O
General-purpose digital I/O /
USCI_B1 slave in/master out in SPI mode, SDA I
2
CdatainI
2
C mode
P2.0/
UCB1STE/UCA1CLK
83 I/O
General-purpose digital I/O /
USCI_B1 slave transmit enable / USCI_A1 clock input/output
P1.7/
UCA1RXD/UCA1SOMI
84 I/O
General-purpose digital I/O /
USCI_A1 receive data input in UART mode, slave out/master in in SPI mode
P1.6/
UCA1TXD/UCA1SIMO
85 I/O
General-purpose digital I/O /
USCI_A1 transmit data output in UART mode, slave in/master out in SPI mode
P1.5/TACLK/ACLK 86 I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/SMCLK 87 I/O
General-purpose digital I/O / input clock TBCLK—Timer_B3 /
submain system clock SMCLK output
P1.3/TBOUTH/SVSOUT 88 I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0
to TB2 / SVS: output of SVS comparator
P1.2/TA1 89 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 90 I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 91 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
DV
CC1
92 Digital supply voltage, positive terminal.
XT2OUT 93 O Output terminal of crystal oscillator XT2
XT2IN 94 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
DV
SS1
95 Digital supply voltage, negative terminal.
TDO/TDI 96 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 97 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 98 I Test mode select. TMS is used as an input port for device programming and test.
TCK 99 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 100 I Reset input or nonmaskable interrupt input port