Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16-Bit 8 MHz I/O number 80

MSP430x461x1, MSP430x461x

MIXED SIGNAL MICROCONTROLLER

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interrupt vector addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 3. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT

WORD

ADDRESS

PRIORITY

Power-Up

External Reset

Watchdog

Flash Memory

WDTIFG

KEYV

(see Note 1 and 5)

Reset 0FFFEh 31, highest

NMI

Oscillator Fault

Flash Memory Access Violation

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1, 2, and 5)

(Non)maskable

0FFFCh 30

Timer_B7 TBCCR0 CCIFG0 (see Note 2) Maskable 0FFFAh 29

Timer_B7

TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,

TBIFG (see Notes 1 and 2)

Maskable 0FFF8h 28

Comparator_A CAIFG Maskable 0FFF6h 27

Watchdog Timer+ WDTIFG Maskable 0FFF4h 26

USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG (see Note 1) Maskable 0FFF2h 25

USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG (see Note 1) Maskable 0FFF0h 24

ADC12 (see Note 6) ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 23

Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0FFECh 22

Timer_A3

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

Maskable 0FFEAh 21

I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 20

USART1 Receive URXIFG1 Maskable 0FFE6h 19

USART1 Transmit UTXIFG1 Maskable 0FFE4h 18

I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 17

Basic Timer1/RTC BTIFG Maskable 0FFE0h 16

DMA DMA0IFG, DMA1IFG, DMA2IFG

(see Notes 1 and 2)

Maskable 0FFDEh 15

Reserved Reserved Maskable 0FFDCh 14

0FFDAh 13

Reserved Reserved (see Note 4)

... ...

Reserved

(see

Note

0FFC0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

5. Access and key violations, KEYV and ACCVIFG, only applicable to F devices.

6. ADC12 is not implemented in MSP430x461x1 devices.