Datasheet

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
40
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P3, P4, P5, P6
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
I
OH(max)
= −1.5 mA (See Note 1) 2.2 V V
CC
−0.25 V
CC
V
High level output voltage
I
OH(max)
= −6 mA (See Note 2) 2.2 V V
CC
−0.6 V
CC
V
V
OH
High-level output voltage
I
OH(max)
= −1.5 mA (See Note 1) 3 V V
CC
−0.25 V
CC
V
I
OH(max)
= −6 mA (See Note 2) 3 V V
CC
−0.6 V
CC
I
OL(max)
= 1.5 mA (See Note 1) 2.2 V V
SS
V
SS
+0.25
V
Low level output voltage
I
OL(max)
= 6 mA (See Note 2) 2.2 V V
SS
V
SS
+0.6
V
V
OL
Low-level output voltage
I
OL(max)
= 1.5 mA (See Note 1) 3 V V
SS
V
SS
+0.25
V
I
OL(max)
= 6 mA (See Note 2) 3 V V
SS
V
SS
+0.6
NOTES: 1. The maximum total current, I
OH(max)
and I
OL(max),
for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, I
OH(max)
and I
OL(max),
for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
(1 x 60y 7)
C
L
= 20 pF,
V
CC
= 2.2 V DC 5
MHz
f
(Px.y)
(1 x 6, 0 y 7)
C
L
=
20
pF
,
I
L
= ±1.5 mA
V
CC
= 3 V DC 7.5
MHz
f
(ACLK)
P1.1/TA0/MCLK,
f
(MCLK)
P1
.
1/TA0/MCLK
,
P1.5/TACLK/ACLK
C
L
= 20 pF f
(
S
y
stem
)
MHz
f
(SMCLK)
P1.5/TACLK/ACLK
P1.4/TBCLK/SMCLK
C
L
20
pF
f
(System)
MHz
P1.5/TACLK/ACLK,
f
(ACLK)
= f
(LFXT1)
= f
(XT1)
40% 60%
P1
.
5/TACLK/ACLK
,
C
L
= 20 pF
f
(ACLK)
= f
(LFXT1)
= f
(LF)
30% 70%
C
L
20
pF
V
CC
= 2.2 V / 3 V
f
(ACLK)
= f
(LFXT1)
50%
P1.1/TA0/MCLK
,
f
(MCLK)
= f
(XT1)
40% 60%
t
(Xdc)
Duty cycle of output frequency
P1
.
1/TA0/MCLK
,
C
L
= 20 pF,
V
CC
= 2.2 V / 3 V
f
(MCLK)
= f
(DCOCLK)
50%−
15 ns
50%
50%+
15 ns
P1.4/TBCLK/SMCLK
,
f
(SMCLK)
= f
(XT2)
40% 60%
P1
.
4/TBCLK/SMCLK
,
C
L
= 20 pF,
V
CC
= 2.2 V / 3 V
f
(SMCLK)
= f
(DCOCLK)
50%−
15 ns
50%
50%+
15 ns