Datasheet

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, P6
PARAMETER V
CC
MIN TYP MAX UNIT
V
Positive going input threshold voltage
2.2 V 1.1 1.5
V
V
IT+
Positive-going input threshold voltage
3 V
1.5 1.9
V
V
Negative going input threshold voltage
2.2 V 0.4 0.9
V
V
IT−
Negative-going input threshold voltage
3 V
0.9 1.3
V
V
Input voltage hysteresis (V V )
2.2 V 0.3 1.1
V
V
hys
Input voltage hysteresis (V
IT+
− V
IT−
)
3 V 0.5 1
V
standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
PARAMETER V
CC
MIN TYP MAX UNIT
V
IL
Low-level input voltage
22V/3V
V
SS
V
SS
+0.6 V
V
IH
High-level input voltage
2.2 V / 3 V
0.8×V
CC
V
CC
V
inputs Px.x, TAx, TBx
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
P t P1 P2 P1 t P2 t l t i i l
2.2 V/3 V 1.5 cycle
t
(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
2.2 V 62
ns
(int)
pg
for
the
interrupt
flag
,
(see
Note
1)
3 V 50
ns
Timer A Timer B capture
TA0, TA1, TA2 2.2 V 62
t
(cap)
Timer_A, Timer_B capture
timing
TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 2)
3 V 50
ns
f
(TAext)
Timer_A, Timer_B clock
frequency externally applied
TACLK TBCLK INCLK: t =t
2.2 V 8
MHz
f
(TBext)
frequency externally applied
to pin
TACLK, TBCLK, INCLK: t
(H)
= t
(L)
3 V 10
MHz
f
(TAint)
Timer_A, Timer_B clock
SMCLK or ACLK signal selected
2.2 V 8
MHz
f
(TBint)
Timer
_
A,
Timer
_
B
clock
frequency
SMCLK or ACLK signal selected
3 V 10
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
(int)
cycle and time parameters are met. It may be set even with
trigger signals shorter than t
(int)
. Both the cycle and timing specifications must be met to ensure the flag is set. t
(int)
is measured in
MCLK cycles.
2. Seven capture/compare registers in ’x44x(1) and three capture/compare registers in ’x43x(1).
leakage current (see Notes 1 and 2)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
I
lkg(P1.x)
Port P1 Port 1: V
(P1.x)
±50
I
lkg(P2.x)
Port P2 Port 2: V
(P2.x)
±50
I
lkg(P3.x)
Leaka
g
e
Port P3 Port 3: V
(P3.x)
2 2 V/3 V
±50
nA
I
lkg(P4.x)
Leakage
current
Port P4 Port 4: V
(P4.x)
2.2 V/3 V
±50
nA
I
lkg(P5.x)
Port P5 Port 5: V
(P5.x)
±50
I
lkg(P6.x)
Port P6 Port 6: V
(P6.x)
±50
NOTES: 1. The leakage current is measured with V
SS
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.