Datasheet
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
USART0
The MSP430x43x(1) and the MSP430x44x(1) have one hardware universal synchronous/asynchronous
receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered
transmit and receive channels.
USART1 (MSP430x44x(1) only)
The MSP430x44x(1) has a second hardware universal synchronous/asynchronous receive transmit (USART1)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
Operation of USART1 is identical to USART0.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER
DEVICE INPUT MODULE INPUT MODULE
MODULE
OUTPUT
OUTPUT PIN NUMBER
PN PZ
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
BLOCK
OUTPUT
SIGNAL
PN PZ
62 - P1.5 82 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK
Timer NA
62 - P1.5 82 - P1.5 TACLK INCLK
67 - P1.0 87 - P1.0 TA0 CCI0A
67 - P1.0 87 - P1.0
66 - P1.1 86 - P1.1 TA0 CCI0B
CCR0
TA0
DV
SS
GND
CCR0 TA0
DV
CC
V
CC
65 - P1.2 85 - P1.2 TA1 CCI1A
14 - P1.2 85 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
ADC12 (internal)
‡
DV
SS
GND
CCR1 TA1
DV
CC
V
CC
59 - P2.0 79 - P2.0 TA2 CCI2A
15 - P1.3 79 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DV
SS
GND
CCR2 TA2
DV
CC
V
CC
‡
Not implemented in MSP430x43x1 and MSP430x44x1 devices.
Timer_B3 (MSP430x43x(1) only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.