Datasheet

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO.
I/O
NAME NO.
I/O
DESCRIPTION
P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O P2.3/TB2 76 I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 57 I/O P2.2/TB1 77 I/O
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 58 I/O P2.1/TB0 78 I/O
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 59 I/O P2.0/TA2 79 I/O
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1 60 I/O P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
62 I/O
P1.5/TACLK/
ACLK
82 I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK
63 I/O
P1.4/TBCLK/
SMCLK
83 I/O
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT
64 I/O
P1.3/TBOUTH/
SVSOUT
84 I/O
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1 65 I/O P1.2/TA1 85 I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.1/TA0/MCLK 66 I/O P1.1/TA0/MCLK 86 I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 67 I/O P1.0/TA0 87 I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 69 I XT2IN 89 I
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI 70 I/O TDO/TDI 90 I/O
Test data output port. TDO/TDI data output or programming data input
terminal
TDI/TCLK 71 I TDI/TCLK 91 I
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TMS 72 I TMS 92 I
Test mode select. TMS is used as an input port for device programming
and test.
TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 74 I RST/NMI 94 I
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0 75 I/O P6.0 95 I/O General-purpose digital I/O
P6.1 76 I/O P6.1 96 I/O General-purpose digital I/O
P6.2 77 I/O P6.2 97 I/O General-purpose digital I/O
AV
SS
78 AV
SS
98
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry.
DV
SS1
79 DV
SS1
99 Digital supply voltage, negative terminal.
AV
CC
80 AV
CC
100
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry;
must not power up prior to DV
CC1
/DV
CC2
.