Datasheet
Table Of Contents
- features
- description
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x4371IPZ
- pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
- pin designation, MSP430x4481IPZ, MSP430x4491IPZ
- pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
- MSP430x43x1 functional block diagram
- MSP430x43x functional block diagram
- MSP430x44x1 functional block diagram
- MSP430x44x functional block diagram
- MSP430x43x1 Terminal Functions
- MSP430x43x Terminal Functions
- MSP430x44x1 Terminal Functions
- MSP430x44x Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- digital I/O
- oscillator and system clock
- brownout, supply voltage supervisor (SVS)
- hardware multiplier (MSP430x44x(1) only)
- watchdog timer (WDT)
- USART0
- USART1 (MSP430x44x(1) only)
- Timer_A3
- Timer_B3 (MSP430x43x(1) only)
- Timer_B7 (MSP430x44x(1) only)
- Comparator_A
- ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
- Basic Timer1
- LCD driver
- peripheral file map
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6
- standard inputs - RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
- inputs Px.x, TAx, TBx
- leakage current
- outputs - ports P1, P2, P3, P4, P5, P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- supply voltage supervisor/monitor (SVS)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0, USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- flash memory
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- port P1, P1.0 to P1.5, input/output with Schmitt trigger
- port P1, P1.6, P1.7, input/output with Schmitt trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
- port P2, P2.1 to P2.3, input/output with Schmitt trigger
- port P2, P2.6 to P2.7, input/output with Schmitt trigger
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- port P4, P4.0 to P4.7, input/output with Schmitt trigger
- port P5, P5.0 to P5.1, input/output with Schmitt trigger
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.7, input/output with Schmitt trigger
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(BOR)
2000 µs
V
CC(start)
dV
CC
/dt ≤ 3 V/s (see Figure 10) 0.7 × V
(B_IT−)
V
V
(B_IT−)
Brownout
dV
CC
/dt ≤ 3 V/s (see Figure 10 through Figure 12) 1.71 V
V
hys(B_IT−)
(see Note 2)
dV
CC
/dt ≤ 3 V/s (see Figure 10) 70 130 180 mV
t
(reset)
Pulse length needed at RST/NMI pin to accepted reset internally,
V
CC
= 2.2 V/3 V
2 µs
NOTES: 1. The current consumption of the brownout module is already included in the I
CC
current consumption data. The voltage level
V
(B_IT−)
+ V
hys(B_IT−)
is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of t
d(BOR)
after V
CC
= V
(B_IT−)
+ V
hys(B_IT−)
. The default FLL+
settings must not be changed until V
CC
≥ V
CC(min)
, where V
CC(min)
is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
typical characteristics
0
1
t
d(BOR)
V
CC
V
(B_IT−)
V
hys(B_IT−)
V
CC(start)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
V
CC(drop)
V
CC
3 V
t
pw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
t
pw
− Pulse Width − µst
pw
− Pulse Width − µs
V
CC
= 3 V
V
CC(drop)
− V
Figure 11. V
CC(drop)
Level With a Square Voltage Drop to Generate a POR/Brownout Signal