Datasheet
Table Of Contents
- features
- description
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x4371IPZ
- pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
- pin designation, MSP430x4481IPZ, MSP430x4491IPZ
- pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
- MSP430x43x1 functional block diagram
- MSP430x43x functional block diagram
- MSP430x44x1 functional block diagram
- MSP430x44x functional block diagram
- MSP430x43x1 Terminal Functions
- MSP430x43x Terminal Functions
- MSP430x44x1 Terminal Functions
- MSP430x44x Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- digital I/O
- oscillator and system clock
- brownout, supply voltage supervisor (SVS)
- hardware multiplier (MSP430x44x(1) only)
- watchdog timer (WDT)
- USART0
- USART1 (MSP430x44x(1) only)
- Timer_A3
- Timer_B3 (MSP430x43x(1) only)
- Timer_B7 (MSP430x44x(1) only)
- Comparator_A
- ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
- Basic Timer1
- LCD driver
- peripheral file map
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6
- standard inputs - RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
- inputs Px.x, TAx, TBx
- leakage current
- outputs - ports P1, P2, P3, P4, P5, P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- supply voltage supervisor/monitor (SVS)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0, USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- flash memory
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- port P1, P1.0 to P1.5, input/output with Schmitt trigger
- port P1, P1.6, P1.7, input/output with Schmitt trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
- port P2, P2.1 to P2.3, input/output with Schmitt trigger
- port P2, P2.6 to P2.7, input/output with Schmitt trigger
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- port P4, P4.0 to P4.7, input/output with Schmitt trigger
- port P5, P5.0 to P5.1, input/output with Schmitt trigger
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.7, input/output with Schmitt trigger
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
I
CAON 1 CARSEL 0 CAREF 0
2.2 V 25 40
A
I
(CC)
CAON=1, CARSEL=0, CAREF=0
3 V 45 60
µA
I
CAON=1, CARSEL=0, CAREF=1/2/3,
2.2 V 30 50
A
I
(Refladder/RefDiode)
CAON=1
,
CARSEL=0
,
CAREF=1/2/3
,
No load at P1.6/CA0 and P1.7/CA1
3 V 45 71
µA
V
(Ref025)
Voltage @ 0.25 V
CC
node
V
CC
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1
2.2 V / 3 V 0.23 0.24 0.25
V
(Ref050)
Voltage @ 0.5 V
CC
node
V
CC
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1
2.2V / 3 V 0.47 0.48 0.5
V
See Figure 6 and Figure 7
PCA0=1, CARSEL=1, CAREF=3,
No load at P1 6/CA0 and P1 7/CA1;
2.2 V 390 480 540
mV
V
(RefVT)
See Figure 6 and Figure 7
No load at P1.6/CA0 and P1.7/CA1;
T
A
= 85°C
3 V 400 490 550
mV
V
IC
Common-mode input
voltage range
CAON=1 2.2 V / 3 V 0 V
CC
−1 V
V
p
−V
S
Offset voltage See Note 2 2.2 V / 3 V −30 30 mV
V
hys
Input hysteresis CAON = 1 2.2 V / 3 V 0 0.7 1.4 mV
T
A
= 25°C,
2.2 V 160 210 300
ns
t
T
A
=
25 C
,
Overdrive 10 mV, without filter: CAF = 0
3 V 80 150 240
ns
t
(response
LH)
T
A
= 25°C
2.2 V 1.4 1.9 3.4
s
T
A
=
25 C
Overdrive 10 mV, with filter: CAF = 1
3 V 0.9 1.5 2.6
µs
T
A
= 25°C
2.2 V 130 210 300
ns
t
T
A
=
25 C
Overdrive 10 mV, without filter: CAF = 0
3 V 80 150 240
ns
t
(response
HL)
T
A
= 25°C,
2.2 V 1.4 1.9 3.4
s
T
A
=
25 C
,
Overdrive 10 mV, with filter: CAF = 1
3 V 0.9 1.5 2.6
µs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to I
lkg(Px.x)
specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.