Datasheet
Table Of Contents
- features
- description
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x4371IPZ
- pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
- pin designation, MSP430x4481IPZ, MSP430x4491IPZ
- pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
- MSP430x43x1 functional block diagram
- MSP430x43x functional block diagram
- MSP430x44x1 functional block diagram
- MSP430x44x functional block diagram
- MSP430x43x1 Terminal Functions
- MSP430x43x Terminal Functions
- MSP430x44x1 Terminal Functions
- MSP430x44x Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- digital I/O
- oscillator and system clock
- brownout, supply voltage supervisor (SVS)
- hardware multiplier (MSP430x44x(1) only)
- watchdog timer (WDT)
- USART0
- USART1 (MSP430x44x(1) only)
- Timer_A3
- Timer_B3 (MSP430x43x(1) only)
- Timer_B7 (MSP430x44x(1) only)
- Comparator_A
- ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
- Basic Timer1
- LCD driver
- peripheral file map
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6
- standard inputs - RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
- inputs Px.x, TAx, TBx
- leakage current
- outputs - ports P1, P2, P3, P4, P5, P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- supply voltage supervisor/monitor (SVS)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0, USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- flash memory
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- port P1, P1.0 to P1.5, input/output with Schmitt trigger
- port P1, P1.6, P1.7, input/output with Schmitt trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
- port P2, P2.1 to P2.3, input/output with Schmitt trigger
- port P2, P2.6 to P2.7, input/output with Schmitt trigger
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- port P4, P4.0 to P4.7, input/output with Schmitt trigger
- port P5, P5.0 to P5.1, input/output with Schmitt trigger
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.7, input/output with Schmitt trigger
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
f = 1 MHz 6
t
d
(
LPM3
)
Delay time
f = 2 MHz
2.2 V/3 V
6
µs
t
d(LPM3)
Delay
time
f = 3 MHz
2.2
V/3
V
6
µs
RAM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRAMh CPU halted (see Note 1) 1.6 V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(33)
Voltage at P5.7/R33 2.5 V
CC
+ 0.2
V
(23)
Analog voltage
Voltage at P5.6/R23
V 3V
[V
(33)
−V
(03)
] × 2/3 + V
(03)
V
V
(13)
Analog voltage
Voltage at P5.5/R13
V
CC
= 3 V
[V
(33)
−V
(03)
] × 1/3 + V
(03)
V
V
(33)
− V
(03)
Voltage at R33 to R03 2.5 V
CC
+ 0.2
I
(R03)
R03 = V
SS
No load at all
±20
I
(R13)
Input leakage
P5.5/R13 = V
CC
/3
segment and
common lines
±20
nA
I
(R23)
pg
P5.6/R23 = 2 × V
CC
/3
common
li
nes,
V
CC
= 3 V
±20
V
(Sxx0)
V
(03)
V
(03)
− 0.1
V
(Sxx1)
Se
g
ment line
I =3µA
V =3V
V
(13)
V
(13)
− 0.1
V
V
(Sxx2)
Segment
line
voltage
I
(Sxx)
= −3 µA, V
CC
= 3 V
V
(23)
V
(23)
− 0.1
V
V
(Sxx3)
V
(33)
V
(33)
+ 0.1