Datasheet
Table Of Contents
- features
- description
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x4371IPZ
- pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
- pin designation, MSP430x4481IPZ, MSP430x4491IPZ
- pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
- MSP430x43x1 functional block diagram
- MSP430x43x functional block diagram
- MSP430x44x1 functional block diagram
- MSP430x44x functional block diagram
- MSP430x43x1 Terminal Functions
- MSP430x43x Terminal Functions
- MSP430x44x1 Terminal Functions
- MSP430x44x Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- digital I/O
- oscillator and system clock
- brownout, supply voltage supervisor (SVS)
- hardware multiplier (MSP430x44x(1) only)
- watchdog timer (WDT)
- USART0
- USART1 (MSP430x44x(1) only)
- Timer_A3
- Timer_B3 (MSP430x43x(1) only)
- Timer_B7 (MSP430x44x(1) only)
- Comparator_A
- ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
- Basic Timer1
- LCD driver
- peripheral file map
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6
- standard inputs - RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
- inputs Px.x, TAx, TBx
- leakage current
- outputs - ports P1, P2, P3, P4, P5, P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- supply voltage supervisor/monitor (SVS)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0, USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- flash memory
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- port P1, P1.0 to P1.5, input/output with Schmitt trigger
- port P1, P1.6, P1.7, input/output with Schmitt trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
- port P2, P2.1 to P2.3, input/output with Schmitt trigger
- port P2, P2.6 to P2.7, input/output with Schmitt trigger
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- port P4, P4.0 to P4.7, input/output with Schmitt trigger
- port P5, P5.0 to P5.1, input/output with Schmitt trigger
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.7, input/output with Schmitt trigger
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History

MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
64
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P4, P4.0 to P4.7, input/output with Schmitt trigger
P4OUT.x
Module X OUT
P4DIR.x
Direction Control
From Module
P4SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x PnOUT.x
Module X
OUT
PnIN.x Module X IN
P4Sel.1 P4DIR.1 P4OUT.1 P4IN.1
P4Sel.2 P4DIR.2 P4OUT.2 P4IN.2
P4Sel.3 P4DIR.3 P4OUT.3 P4IN.3
P4Sel.4 P4DIR.4 P4OUT.4 P4IN.4
P4Sel.5 P4DIR.5 P4OUT.5 P4IN.5
P4Sel.0 P4DIR.0 P4OUT.0 P4IN.0
Segment xx
0: Port active
1: Segment xx function active
P4Sel.6 P4DIR.6
P4Sel.7 P4DIR.7
P4DIR.6
P4DIR.7
P4OUT.6
P4OUT.7
P4IN.6
P4IN.7 unused
unused
unused
Module X IN
P4IN.x
0< x< 7Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
Direction
From Module
Control
DV
SS
†
UTXD1
‡
DV
SS
DV
SS
DV
SS
DV
SS
Port/LCD
§
x43x(1)IPN
80-Pin
QFP:
P4.7/S2
P4.6/S3
P4.5/S4
P4.3/S6
P4.4/S5
P4.2/S7
P4.1/S8
P4.0/S9
x43x(1)IPZ
100-Pin
QFP:
P4.7/S34
P4.6/S35
P4.5/S36
P4.3/S37
P4.4/S38
P4.2/S39
P4.0
P4.1
x44x(1)
P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SMO1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
P4.1/URXD1
P4.0/UTXD1
P4DIR.0
†
DV
CC‡
P4DIR.1
†
DV
SS‡
P4DIR.2
†
DV
SS‡
P4DIR3.
†
DCM_SIMO1
‡
P4DIR4.
†
DCM_SOMI
1‡
P4DIR5.
†
DCM_UCLK1
‡
DV
SS
†
SIMO1(out)
‡
DV
SS
†
SOMI1(out)
‡
DV
SS
†
UCLK1(out)
‡
unused†
URXD1
‡
unused†
STE1(in)‡
unused†
SIMO1(in)‡
unused
SOMI1(in)‡
unused†
UCLK1(in)‡
†
Signal at MSP430x43x(1)
‡
Signal at MSP430x44x(1)
DEVICE
PORT BITS PORT FUNCTION LCD SEG. FUNCTION
x43x(1)IPN 80-pin QFP P4.0 . . .P4.7 LCDM < 020h LCDM ≥ 020h
x43x(1)IPZ 100-pin QFP P4.2 . . .P4.5 LCDM < 0E0h LCDM ≥ 0E0h
x44x(1)IPZ 100-pin QFP P4.6 . . .P4.7 LCDM < 0C0h LCDM ≥ 0C0h