Datasheet
Table Of Contents
- features
- description
- DEVELOPMENT TOOL SUPPORT
- pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x4371IPZ
- pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
- pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
- pin designation, MSP430x4481IPZ, MSP430x4491IPZ
- pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
- MSP430x43x1 functional block diagram
- MSP430x43x functional block diagram
- MSP430x44x1 functional block diagram
- MSP430x44x functional block diagram
- MSP430x43x1 Terminal Functions
- MSP430x43x Terminal Functions
- MSP430x44x1 Terminal Functions
- MSP430x44x Terminal Functions
- short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
- special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
- memory organization
- bootstrap loader (BSL)
- flash memory
- peripherals
- digital I/O
- oscillator and system clock
- brownout, supply voltage supervisor (SVS)
- hardware multiplier (MSP430x44x(1) only)
- watchdog timer (WDT)
- USART0
- USART1 (MSP430x44x(1) only)
- Timer_A3
- Timer_B3 (MSP430x43x(1) only)
- Timer_B7 (MSP430x44x(1) only)
- Comparator_A
- ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
- Basic Timer1
- LCD driver
- peripheral file map
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6
- standard inputs - RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
- inputs Px.x, TAx, TBx
- leakage current
- outputs - ports P1, P2, P3, P4, P5, P6
- output frequency
- wake-up LPM3
- RAM
- LCD
- Comparator_A
- POR/brownout reset (BOR)
- supply voltage supervisor/monitor (SVS)
- DCO
- crystal oscillator, LFXT1 oscillator
- crystal oscillator, XT2 oscillator
- USART0, USART1
- 12-bit ADC, power supply and input range conditions
- 12-bit ADC, external reference
- 12-bit ADC, built-in reference
- 12-bit ADC, timing parameters
- 12-bit ADC, linearity parameters
- 12-bit ADC, temperature sensor and built-in VMID
- flash memory
- JTAG interface
- JTAG fuse
- APPLICATION INFORMATION
- input/output schematics
- port P1, P1.0 to P1.5, input/output with Schmitt trigger
- port P1, P1.6, P1.7, input/output with Schmitt trigger
- port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
- port P2, P2.1 to P2.3, input/output with Schmitt trigger
- port P2, P2.6 to P2.7, input/output with Schmitt trigger
- port P3, P3.0 to P3.3, input/output with Schmitt trigger
- port P3, P3.4 to P3.7, input/output with Schmitt trigger
- port P4, P4.0 to P4.7, input/output with Schmitt trigger
- port P5, P5.0 to P5.1, input/output with Schmitt trigger
- port P5, P5.2 to P5.4, input/output with Schmitt trigger
- port P5, P5.5 to P5.7, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.0 to P6.6, input/output with Schmitt trigger
- port P6, P6.7, input/output with Schmitt trigger
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematics
- Data Sheet Revision History
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics
port P1, P1.0 to P1.5, input/output with Schmitt trigger
P1OUT.x
Module X OUT
P1DIR.x
Direction Control
From Module
P1SEL.x
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.x
P1IFG.x
P1IRQ.x
P1.x
EN
Set
Q
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
Keeper
CAPD.x
Note:
0< x< 5
Note: Port function is active if CAPD.x = 0
PnSel.x PnDIR.x
Direction
From Module
PnOUT.x
Module X
OUT
PnIN.x
PnIE.x
PnIFG.x
PnIES.x
Module X IN
P1Sel.1 P1DIR.1 P1OUT.1 P1IN.1 P1IE.1 P1IFG.1 P1IES.1
P1Sel.2 P1DIR.2 P1OUT.2 P1IN.2 P1IE.2 P1IFG.2 P1IES.2
P1Sel.3 P1DIR.3 P1OUT.3 P1IN.3 P1IE.3 P1IFG.3 P1IES.3
P1Sel.4 P1DIR.4
P1OUT.4 P1IN.4 P1IE.4 P1IFG.4 P1IES.4
P1Sel.5 P1DIR.5 P1OUT.5 P1IN.5 P1IE.5 P1IFG.5 P1IES.5
P1Sel.0
P1DIR.0
P1OUT.0
P1IN.0
P1IE.0 P1IFG.0 P1IES.0
SVSOUT
Out0 sig.
Out1 sig.
CCI0A
CCI1A
TBOUTH
TBCLK
TACLK
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
P1DIR.0
SMCLK
ACLK
MCLK
Module X IN
P1IN.x
P1.5/TACLK/ACLK
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.4/TBCLK/SMCLK
P1.3/TBOUTH/SVSOUT
CCI0B
†
†
†
†
†
†
Control
‡
‡
†
Timer_A
‡
Timer_B