Datasheet

MSP430F42x0
MIXED SIGNAL MICROCONTROLLER
SLAS455D − MARCH 2005 − REVISED APRIL 2007
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature
Number SLAU056.
oscillator and system clock
The clock system in the MSP430F42x0 family of devices is supported by the FLL+ module that includes support
for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module
provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The CPU begins code execution after the brownout circuit releases the device reset. However,
V
CC
may not have ramped to V
CC(min)
at that time. The user must insure the default FLL+ settings are not
changed until V
CC
reaches V
CC(min)
.
digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P5 and P6:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts.
LCD driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2−MUX, 3−MUX, and 4−MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.
watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.