Datasheet
Table Of Contents
- features
- description
- pin designation, DL package
- pin designation, RGZ package
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC
- SCHMITT-trigger inputs
- inputs Px.x, TAx
- leakage current
- outputs
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- POR/brownout reset
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16_A, power supply and recommended operating conditions
- SD16_A, input range
- SD16_A, performance (fSD16 = 30kHz, SD16REFON = 1, SD16BUFx = 01)
- SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00)
- SD16_A, temperature sensor
- SD16_A, built-in voltage reference
- SD16_A, reference output buffer
- SD16_A, external reference input
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications
- Flash Memory
- JTAG Interface
- JTAG Fuse
- input/output schematics
- Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger
- Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions
- Port P2 pin schematic: P2.0 to P2.7, input/output with Schmitt−trigger, LCD and analog functions
- Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCDfunctions
- Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions
- Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- Data Sheet Revision History
- Corrections to MSP430F42x0 Data Sheet (SLAS455D)
MSP430F42x0
MIXED SIGNAL MICROCONTROLLER
SLAS455D − MARCH 2005 − REVISED APRIL 2007
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment 0
w/ Interrupt Vectors
Segment 1
Segment 2
Segment n-1
Segment n†
Segment A
Segment B
Main
Memory
Information
Memory
32KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
08400h
083FFh
08200h
081FFh
08000h
010FFh
01080h
0107Fh
01000h
24KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0A400h
0A3FFh
0A200h
0A1FFh
0A000h
010FFh
01080h
0107Fh
01000h
16KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0C400h
0C3FFh
0C200h
0C1FFh
0C000h
010FFh
01080h
0107Fh
01000h