Datasheet

MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A − APRIL 2004 − REVISED JUNE 2007
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F42x Terminal Functions (Continued)
TERMINAL
PN
I/O DESCRIPTION
NAME NO.
R13 41 I Input port of third most positive analog LCD level (V4 or V3)
R23 42 I Input port of second most positive analog LCD level (V2)
R33 43 O Output port of most positive analog LCD level (V1)
P2.1/UCLK0/S24 44 I/O
General-purpose digital I/O / external clock input-USART0/UART or SPI mode, clock output—USART0/SPI
mode / LCD segment output 24 (See Note 1)
P2.0/TA2/S25 45 I/O
General-purpose digital I/O / Timer_A Capture: CCI2A input, Compare: Out2 output / LCD segment output
25 (See Note 1)
P1.7/SOMI0/S26 46 I/O
General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 26
(See Note 1)
P1.6/SIMO0/S27 47 I/O
General-purpose digital I/O / slave in/master out of USART0/SPI mode / LCD segment output 27
(See Note 1)
P1.5/TACLK/
ACLK/S28
48 I/O
General-purpose digital I/O / Timer_A and SD16 clock signal TACLK input / ACLK output (divided by 1,
2, 4, or 8) / LCD segment output 28 (See Note 1)
P1.4/S29 49 I/O General-purpose digital I/O / LCD segment output 29 (See Note 1)
P1.3/SVSOUT/
S30
50 I/O General-purpose digital I/O / SVS: output of SVS comparator / LCD segment output 30 (See Note 1)
P1.2/TA1/S31 51 I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A, CCI1B input, Compare: Out1 output / LCD segment
output 31 (See Note 1)
P1.1/TA0/MCLK 52 I/O
General-purpose digital I/O / Timer_A, Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 53 I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, Compare: Out0 output / BSL transmit
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI.
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
TCK 57 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 58 I Reset input or nonmaskable interrupt input port
P2.5/URXD0 59 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 60 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/SVSIN 61 I/O General-purpose digital I/O / Analog input to brownout, supply voltage supervisor
AV
SS
62
Analog supply voltage, negative terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry.
DV
SS
63 Digital supply voltage, negative terminal
AV
CC
64
Analog supply voltage, positive terminal. Supplies SD16, SVS, brownout, oscillator, and LCD resistive
divider circuitry; must not power up prior to DV
CC
.
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.