Datasheet
Table Of Contents
- features
- description
- Available Options
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics over recommended operating free-air temperature
- supply current into AVCC + DVCC excluding external
- current consumption of active mode versus system frequency
- current consumption of active mode versus supply voltage
- Schmitt-trigger inputs -- Ports P1 and P2, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx
- leakage current
- outputs -- Ports P1 and P2
- output frequency
- wake-up LPM3
- RAM
- LCD
- USART0
- POR brownout, reset
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16, power supply and recommended operating conditions
- SD16, analog input range
- SD16, analog performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1)
- SD16, built-in voltage reference
- SD16, built-in reference output buffer
- SD16, external reference input
- flash memory
- JTAG interface
- JTAG fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.1, input/output with Schmitt trigger
- Port P1, P1.2 to P1.7, input/output with Schmitt trigger
- Port P2, P2.0 to P2.1, input/output with Schmitt trigger
- Port P2, P2.2 to P2.5, input/output with Schmitt trigger
- Port P2, unbonded GPIOs P2.6 and P2.7
- JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
MSP430F42xA
MIXED SIGNAL MICROCONTROLLER
SLAS587 -- FEBRUARY 2008
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External reset
Watchdog
Flash memory
PC out-of-range (see Note 4)
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
0FFFAh 13
SD16
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0FFF8h 12
0FFF6h 11
Watchdog timer WDTIFG Maskable 0FFF4h 10
USART0 receive URXIFG0 Maskable 0FFF2h 9
USART0 transmit UTXIFG0 Maskable 0FFF0h 8
0FFEEh 7
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6
Timer_A3
TACCR1 and TACCR2
CCIFGs, and TACTL TAIFG
(see Notes 1 and 2)
Maskable 0FFEAh 5
I/O port P1 (eight flags)
P1IFG.0toP1IFG.7
(see Notes 1 and 2)
Maskable 0FFE8h 4
0FFE6h 3
0FFE4h 2
I/O port P2 (eight flags)
P2IFG.0toP2IFG.7
(see Notes 1 and 2)
Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges (from 0600h to 0BFFh).