Datasheet
Table Of Contents
- features
- description
- Available Options
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics over recommended operating free-air temperature
- supply current into AVCC + DVCC excluding external
- current consumption of active mode versus system frequency
- current consumption of active mode versus supply voltage
- Schmitt-trigger inputs -- Ports P1 and P2, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx
- leakage current
- outputs -- Ports P1 and P2
- output frequency
- wake-up LPM3
- RAM
- LCD
- USART0
- POR brownout, reset
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16, power supply and recommended operating conditions
- SD16, analog input range
- SD16, analog performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1)
- SD16, built-in voltage reference
- SD16, built-in reference output buffer
- SD16, external reference input
- flash memory
- JTAG interface
- JTAG fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.1, input/output with Schmitt trigger
- Port P1, P1.2 to P1.7, input/output with Schmitt trigger
- Port P2, P2.0 to P2.1, input/output with Schmitt trigger
- Port P2, P2.2 to P2.5, input/output with Schmitt trigger
- Port P2, unbonded GPIOs P2.6 and P2.7
- JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History

MSP430F42xA
MIXED SIGNAL MICROCONTROLLER
SLAS587 -- FEBRUARY 2008
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.0 to P2.1, input/output with Schmitt trigger
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x
EN
Set
Q
0
1
1
0
PnSel.x PnDIR.x
Dir . Control
from module
PnOUT.x
Module X
OUT
PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
0: Port active
1: Segment xx function active
P2Sel.0 P2DIR.0
P2Sel.1 P2DIR.1
P2DIR.0
DCM_UCLK
P2OUT.0
P2OUT.1
P2IN.0
P2IN.1 UCLK0(i)
Out2sig.
UCLK0(o)
P2IE.0
P2IE.1
P2IFG.0
P2IFG.1
P2IES.0
P2IES.1
Module X IN
P2IN.x
Pad Logic
0: Input
1: Output
Bus
Keeper
CCI2A
Port/LCD
Port/LCD
Segment xx
P2.0/TA2/S25
P2.1/UCLK0/S24
†
†
Timer_A3
‡
USART0
‡
†
‡
Segment
S25
S24
0: LCDM
<0E0h
1: LCDM
≥ 0E0h
NOTE: 0 ≤ x ≤ 1.
Port Function is Active if Port/LCD = 0
SYNC
MM
STC
STE
DCM_UCLK
Direction Control for UCLK0