Datasheet
Table Of Contents
- features
- description
- Available Options
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics over recommended operating free-air temperature
- supply current into AVCC + DVCC excluding external
- current consumption of active mode versus system frequency
- current consumption of active mode versus supply voltage
- Schmitt-trigger inputs -- Ports P1 and P2, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx
- leakage current
- outputs -- Ports P1 and P2
- output frequency
- wake-up LPM3
- RAM
- LCD
- USART0
- POR brownout, reset
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16, power supply and recommended operating conditions
- SD16, analog input range
- SD16, analog performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1)
- SD16, built-in voltage reference
- SD16, built-in reference output buffer
- SD16, external reference input
- flash memory
- JTAG interface
- JTAG fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.1, input/output with Schmitt trigger
- Port P1, P1.2 to P1.7, input/output with Schmitt trigger
- Port P2, P2.0 to P2.1, input/output with Schmitt trigger
- Port P2, P2.2 to P2.5, input/output with Schmitt trigger
- Port P2, unbonded GPIOs P2.6 and P2.7
- JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
MSP430F42xA
MIXED SIGNAL MICROCONTROLLER
SLAS587 -- FEBRUARY 2008
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.1, input/output with Schmitt trigger
P1OUT.x
Module X OUT
P1DIR.x
Direction Control
From Module
P1SEL.x
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.x
P1IFG.x
P1IRQ.x
EN
Set
Q
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
CAPD.x
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x
Module X
OUT
PnIN.x
PnIE.x
PnIFG.x
PnIES.x
Module X IN
P1SEL.1 P1DIR.1 P1OUT.1 P1IN.1 P1IE.1 P1IFG.1 P1IES.1
P1SEL.0
P1DIR.0
P1OUT.0
P1IN.0
P1IE.0 P1IFG.0 P1IES.0
P1DIR.1
P1DIR.0
MCLK
Module X IN
P1IN.x
P1.0/TA0
P1.1/TA0/MCLK
Control
NOTE: 0 ≤ x ≤ 1.
Port Function is Active if CAPD.x = 0
†
Timer_A3
Out0 Sig.
†
CCI0A
†
CCI0B
†
CAPD.x
DVSS
DVSS