Datasheet
Table Of Contents
- features
- description
- Available Options
- pin designation
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics over recommended operating free-air temperature
- supply current into AVCC + DVCC excluding external
- current consumption of active mode versus system frequency
- current consumption of active mode versus supply voltage
- Schmitt-trigger inputs -- Ports P1 and P2, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
- inputs Px.x, TAx
- leakage current
- outputs -- Ports P1 and P2
- output frequency
- wake-up LPM3
- RAM
- LCD
- USART0
- POR brownout, reset
- SVS (supply voltage supervisor/monitor)
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16, power supply and recommended operating conditions
- SD16, analog input range
- SD16, analog performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1)
- SD16, built-in voltage reference
- SD16, built-in reference output buffer
- SD16, external reference input
- flash memory
- JTAG interface
- JTAG fuse
- Application Information
- input/output schematic
- Port P1, P1.0 to P1.1, input/output with Schmitt trigger
- Port P1, P1.2 to P1.7, input/output with Schmitt trigger
- Port P2, P2.0 to P2.1, input/output with Schmitt trigger
- Port P2, P2.2 to P2.5, input/output with Schmitt trigger
- Port P2, unbonded GPIOs P2.6 and P2.7
- JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output
- JTAG fuse check mode
- input/output schematic
- Data Sheet Revision History
MSP430F42xA
MIXED SIGNAL MICROCONTROLLER
SLAS587 -- FEBRUARY 2008
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
module enable registers 1 and 2
7654 0
UTXE0
32 1
rw–0 rw–0
Address
04h
URXE0
USPIE0
URXE0: USART0: UART mode receive enable
UTXE0: USART0: UART mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable
7654 0321
Address
05h
Legend: rw--0,1: Bit can be read and written. It Is reset or set by PUC.
rw--(0,1): Bit can be read and written. It Is reset or set by POR.
SFR Bit Not Present in Device.
memory organization
MSP430F423A MSP430F425A MSP430F427A
Memory
Interrupt vector
Code memory
Size
Flash
Flash
8KB
0FFFFh to 0FFE0h
0FFFFh to 0E000h
16KB
0FFFFh to 0FFE0h
0FFFFh to 0C000h
32KB
0FFFFh to 0FFE0h
0FFFFh to 08000h
Information memory Size 256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
Boot memory Size 1kB
0FFFh to 0C00h
1kB
0FFFh to 0C00h
1kB
0FFFh to 0C00h
RAM Size 256 Byte
02FFh to 0200h
512 Byte
03FFh to 0200h
1KB
05FFh to 0200h
Peripherals 16 bit
8bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the application report Features of the MSP430
Bootstrap Loader, literature number SLAA089.
BSL FUNCTION PM PACKAGE PINS
Data transmit 53 - P1.0
Data receive 52 - P1.1