Datasheet

MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, and P6
PARAMETER V
CC
MIN MAX UNIT
V
Positive going input threshold voltage
2.2 V 1.1 1.5
V
V
IT+
Positive-going input threshold voltage
3 V
1.5 1.9
V
V
Negative going input threshold voltage
2.2 V 0.4 0.9
V
V
IT−
Negative-going input threshold voltage
3 V
0.9 1.3
V
V
Input voltage hysteresis (V V )
2.2 V 0.3 1.1
V
V
hys
Input voltage hysteresis (V
IT+
− V
IT−
)
3 V 0.45 1
V
standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER V
CC
MIN MAX UNIT
V
IL
Low-level input voltage
2 2 V/3 V
V
SS
V
SS
+0.6 V
V
IH
High-level input voltage
2.2 V/3 V
0.8×V
CC
V
CC
V
inputs Px.x, TAx/TAx.x
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
Port P1, P2: P1.x to P2.x, External
2.2 V/3 V 1.5 cycle
t
(int)
External interrupt timing
Port
P1
,
P2:
P1
.
x
to
P2
.
x
,
External
trigger signal for the interrupt flag
(N )
2.2 V 62
ns
(int)
pg
gg g p g
(see Note 1)
3 V 50
ns
t
()
Timer A capture timing
TAx/TAx y
2.2 V 62
ns
t
(cap)
Timer_A, capture timing TAx/TAx.y
3 V 50
ns
f
Timer_A clock frequenc
y
externall
y
applied
TACLK/TAxCLK INCLK t =t
2.2 V 8
MHz
f
(TAext)
Timer
_
A
clock
frequency
externally
applied
to pin
TACLK/TAxCLK, INCLK
t
(H)
= t
(L)
3 V 10
MHz
f
Timer A clock frequency
SMCLK or ACLK signal selected
2.2 V 8
MHz
f
(TAint)
Timer_A clock frequency SMCLK or ACLK signal selected
3 V 10
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
(int)
cycle and time parameters are met. It may be set even with
trigger signals shorter than t
(int)
. Both the cycle and timing specifications must be met to ensure the flag is set. t
(int)
is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER TEST CONDITIONS V
CC
MIN MAX UNIT
I
lkg(P1.x)
Port P1 V
(P1.x)
(see Note 2) ±50
I
lkg(P2.x)
Port P2 V
(P2.x)
(see Note 2) ±50
I
lkg(P3.x)
Leakage current
Port P3 V
(P3.x)
(see Note 2)
2 2 V/3 V
±50
nA
I
lkg(P4.x)
Leakage current
Port P4 V
(P4.x)
(see Note 2)
2.2 V/3 V
±50
nA
I
lkg(P5.x)
Port P5 V
(P5.x)
(see Note 2) ±50
I
lkg(P6.x)
Port P6 V
(P6.x)
(see Note 2) ±50
NOTES: 1. The leakage current is measured with V
SS
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.