Datasheet

MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7654 0
OFIE WDTIE
321
rw-0 rw-0 rw-0
Address
0h ACCVIE NMIIE
rw-0
7654 0321
Address
1h BTIE
rw-0
WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is
configured in interval timer mode.
OFIE: Oscillator fault interrupt enable
NMIIE: Nonmaskable interrupt enable
ACCVIE: Flash access violation interrupt enable
BTIE: Basic Timer1 interrupt enable
interrupt flag register 1 and 2
7654 0
OFIFG WDTIFG
321
rw-0 rw-1 rw-(0)
Address
02h NMIIFG
7654 0321
Address
3h BTIFG
rw-0
WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with V
CC
power-up,
or a reset condition at the RST
/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST
/NMI pin
BTIFG: Basic Timer1 interrupt flag
module enable registers 1 and 2
7654 0321
Address
04h/05h
Legend: rw−0,1: Bit Can Be Read and Written. It Is Reset or Set by PUC.
rw−(0,1): Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device.