Datasheet
MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
watchdog timer (WDT+)
The primary function of the W DT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
Basic Timer1 and Real-Time Clock (RTC)
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time
clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year
correction.
LCD_A driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2--MUX, 3--MUX, and 4--MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.
Timer0_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER
DE
V
ICE INPUT MODULE MODULE
MODULE
O
U
T
P
U
T
OUTPUT PIN NUMBER
PM RGZ
D
E
V
I
C
E
I
N
P
U
T
SIGNAL
M
O
D
U
L
E
INPUT NAME
M
O
D
U
L
E
BLOCK
OUTPUT
SIGNAL
PM RGZ
48 -- P1.5
46 -- P1.7
35 -- P1.5
33 -- P1.7
TA0CLK TACLK
ACLK ACLK
Timer N
A
SMCLK SMCLK
T
i
m
e
r
N
A
48 -- P1.5 35 -- P1.5 TA0CLK TACLK
53 -- P1.0 37 -- P1.0 TA0.0 CCI0A 53 -- P1.0 37 -- P1.0
52 -- P1.1 36 -- P1.1 TA0.0 CCI0B
C
C
R
0
T
A
0
32 -- P3.3 --
DV
SS
GND
CCR0 T
A
0
DV
CC
V
CC
51 -- P1.2 -- TA0.1 CCI1A 51 -- P1.2
CAOUT (internal) CCI1B
C
C
R
1
T
A
1
ADC10 (internal) ADC10 (internal)
DV
SS
GND
CCR1 T
A
1
DV
CC
V
CC
45 -- P7.6 -- TA0.2 CCI2A 45 -- P7.6 --
ACLK (internal) CCI2B
C
C
R
2
T
A
2
DV
SS
GND
CCR2 T
A
2
DV
CC
V
CC