Datasheet

R
Load
AV
CC
C
Load
= 100pF
2
DAC Output
R
O/P(DAC12.x)
I
Load
Conversion 1 Conversion 2
V
OUT
Conversion 3
Glitch
Energy
+/− 1/2 LSB
+/− 1/2 LSB
t
settleLH
t
settleHL
= 3 kΩ
MSP430F261x
MSP430F241x
SLAS541K –JUNE 2007–REVISED NOVEMBER 2012 www.ti.com
12-Bit DAC Dynamic Specifications
V
REF
= V
CC
, DAC12IR = 1 (see Figure 45 and Figure 46), over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
DAC12AMPx = 0 → {2, 3, 4} 60 120
DAC12_xDAT = 800h,
t
ON
DAC12 on-time Error
V(O)
< ±0.5 LSB
(1)
(see DAC12AMPx = 0 → {5, 6} 2.2 V, 3 V 15 30 µs
Figure 45)
DAC12AMPx = 0 → 7 6 12
DAC12AMPx = 2 100 200
Settling time, DAC12_xDAT =
t
S(FS)
DAC12AMPx = 3, 5 2.2 V, 3 V 40 80 µs
full scale 80h → F7Fh → 80h
DAC12AMPx = 4, 6, 7 15 30
DAC12AMPx = 2 5
DAC12_xDAT =
Settling time,
t
S(C-C)
3F8h → 408h → 3F8h DAC12AMPx = 3, 5 2.2 V, 3 V 2 µs
code to code
BF8h → C08h → BF8h
DAC12AMPx = 4, 6, 7 1
DAC12AMPx = 2 0.05 0.12
DAC12_xDAT =
SR Slew rate
(2)
DAC12AMPx = 3, 5 2.2 V, 3 V 0.35 0.7 V/µs
80h → F7Fh → 80h
DAC12AMPx = 4, 6, 7 1.5 2.7
DAC12AMPx = 2 600
Glitch energy, full DAC12_xDAT =
DAC12AMPx = 3, 5 2.2 V, 3 V 150 nV-s
scale 80h → F7Fh → 80h
DAC12AMPx = 4, 6, 7 30
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1,
40
DAC12_xDAT = 800h
3-dB bandwidth,
V
DC
= 1.5 V, V
AC
DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1,
BW
-3dB
2.2 V, 3 V 180 kHz
= 0.1 V
PP
(see DAC12_xDAT = 800h
Figure 47)
DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1,
550
DAC12_xDAT = 800h
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, R
Load
= 3 kΩ, -80
Channel-to-
f
DAC12_1OUT
= 10 kHz, Duty cycle = 50%
channel
2.2 V, 3 V dB
crosstalk
(1)
(see
DAC12_0DAT = 80h ↔ F7Fh, R
Load
= 3 kΩ,
Figure 48)
DAC12_1DAT = 800h, No load, f
DAC12_0OUT
= 10 kHz, -80
Duty cycle = 50%
(1) R
Load
and C
Load
are connected to AV
SS
(not AV
CC
/2) in Figure 45.
(2) Slew rate applies to output voltage steps ≥ 200 mV.
Figure 45. Settling Time and Glitch Energy Testing
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