Datasheet
MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547 -- JUNE 2007
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timer_B3 (MSP430F23x devices)
Timer_B3 is a 16-bit timer/counter with seven capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3 Signal Connections
Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number
43 - P4.7 TBCLK TBCLK
ACLK ACLK
T
i
m
e
r
N
A
SMCLK SMCLK
Timer N
A
43 - P4.7 TBCLK INCLK
36 - P4.0 TB0 CCI0A
36 - P4.0
36 - P4.0 TB0 CCI0B
C
C
R
0
T
B
0
ADC12 (internal)
DV
SS
GND
CCR0 TB0
DV
CC
V
CC
37 - P4.1 TB1 CCI1A
37 - P4.1
37 - P4.1 TB1 CCI1B
C
C
R
1
T
B
1
ADC12 (internal)
DV
SS
GND
CCR1 TB1
DV
CC
V
CC
38 - P4.2 TB2 CCI2A
38 - P4.2
38 - P4.2 TB2 CCI2B
C
C
R
2
T
B
2
DV
SS
GND
CCR2 TB2
DV
CC
V
CC
USCI
The universal serial communicating interface (USCI ) modules are used for serial data communication. The
USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I
2
C and asynchronous
combination protocols like UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
The USCI A module provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
The USCI B module provides support for SPI (3 or 4 pin) and I
2
C.
comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog--to--digital conversions,
battery--voltage supervision, and monitoring of external analog signals.
ADC12 (F23x, F24x, and F2410 devices only)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, s ample select c ontrol, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
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