Datasheet

MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547 -- JUNE 2007
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
digital I/O
There are up to six 8-bit I/O ports implemented—ports P1 through P6:
D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.
D Each I/O has an individually programmable pullup/pulldown resistor.
watchdog timer+
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number
12 - P1.0 TACLK TACLK
ACLK ACLK
T
i
m
e
r
N
A
SMCLK SMCLK
Timer N
A
21 - P2.1 TAINCLK INCLK
13 - P1.1 TA0 CCI0A
13 - P1.1
22 - P2.2 TA0 CCI0B
C
C
R
0
T
A
0
17 - P1.5
DV
SS
GND
CCR0 T
A
0
27 - P2.7
DV
CC
V
CC
14 - P1.2 TA1 CCI1A
14 - P1.2
CAOUT (internal) CCI1B
C
C
R
1
T
A
1
18 - P1.6
DV
SS
GND
CCR1 T
A
1
23 - P2.3
DV
CC
V
CC
ADC12{ (internal)
15 - P1.3 TA2 CCI2A
15 - P1.3
ACLK (internal) CCI2B
C
C
R
2
T
A
2
19 - P1.7
DV
SS
GND
CCR2 T
A
2
24 - P2.4
DV
CC
V
CC
†
Not available in the 24x1 family devices
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