Datasheet
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
Direction
0: Input
1: Output
D
EN
DVSS
DVCC
Pad Logic
1
1
0
1
0
1
0
P4SEL.x
P4DIR.x
P4IN.x
Module X IN
Module X OUT
P4OUT.x
P4REN.x
MSP430F23x
MSP430F24x(1)
MSP430F2410
www.ti.com
SLAS547I –JUNE 2007–REVISED DECEMBER 2012
Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger
Table 24. Port P4.0 to P4.7 Pin Functions
CONTROL BITS / SIGNALS
PIN NAME (P4.x) x FUNCTION
P4DIR.x P4SEL.x
P4.0 (I/O) I: 0; O: 1 0
P4.0/TB0 0 Timer_B7.CCI0A and Timer_B7.CCI0B 0 1
Timer_B7.TB0 1 1
P4.1 (I/O) I: 0; O: 1 0
P4.1/TB1 1 Timer_B7.CCI1A and Timer_B7.CCI1B 0 1
Timer_B7.TB1 1 1
P4.2 (I/O) I: 0; O: 1 0
P4.2/TB2 2 Timer_B7.CCI2A and Timer_B7.CCI2B 0 1
Timer_B7.TB2 1 1
P4.3 (I/O) I: 0; O: 1 0
P4.3/TB3
(1)
3 Timer_B7.CCI3A and Timer_B7.CCI3B
(1)
0 1
Timer_B7.TB3
(1)
1 1
P4.4 (I/O) I: 0; O: 1 0
P4.4/TB4
(1)
4 Timer_B7.CCI4A and Timer_B7.CCI4B
(1)
0 1
Timer_B7.TB4
(1)
1 1
P4.5 (I/O) I: 0; O: 1 0
P4.5/TB5
(1)
5 Timer_B7.CCI5A and Timer_B7.CCI5B
(1)
0 1
Timer_B7.TB5
(1)
1 1
P4.6 (I/O) I: 0; O: 1 0
P4.6/TB6
(1)
6 Timer_B7.CCI6A and Timer_B7.CCI6B
(1)
0 1
Timer_B7.TB6
(1)
1 1
P4.7 (I/O) I: 0; O: 1 0
P4.7/TBCLK 7
Timer_B7.TBCLK 0 1
(1) MSP430F24x and MSP430F24x1 devices only
Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback 73