Datasheet

Direction
0: Input
1: Output
P3SEL.x
P3DIR.x
P3IN.x
D
EN
Module X IN
Module X OUT
P3OUT.x
DVSS
DVCC
Pad Logic
1
1
0
1
0
1
0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P3REN.x
Module direction
MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547I –JUNE 2007–REVISED DECEMBER 2012 www.ti.com
Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger
Table 23. Port P3.0 to P3.7 Pin Functions
CONTROL BITS /
SIGNALS
(1)
PIN NAME (P3.x) x FUNCTION
P3DIR.x P3SEL.x
P3.0 (I/O) I: 0; O: 1 0
P3.0/UCB0STE/UCA0CLK 0
UCB0STE/UCA0CLK
(2)(3)
X 1
P3.1 (I/O) I: 0; O: 1 0
P3.1/UCB0SIMO/UCB0SDA 1
UCB0SIMO/UCB0SDA
(2)(4)
X 1
P3.2 (I/O) I: 0; O: 1 0
P3.2/UCB0SOMI/UCB0SCL 2
UCB0SOMI/UCB0SCL
(2)(4)
X 1
P3.3 (I/O) I: 0; O: 1 0
P3.3/UCB0CLK/UCA0STE 3
UCB0CLK/UCA0STE
(2)
X 1
P3.4 (I/O) I: 0; O: 1 0
P3.4/UCA0TXD/UCA0SIMO 4
UCA0TXD/UCA0SIMO
(2)
X 1
P3.5 (I/O) I: 0; O: 1 0
P3.5/UCA0RXD/UCA0SOMI 5
UCA0RXD/UCA0SOMI
(2)
X 1
P3.6 (I/O) I: 0; O: 1 0
P3.6/UCA1TXD
(5)
/UCA1SIMO
(5)
6
UCA1TXD
(5)
/UCA1SIMO
(5)(2)
X 1
P3.7 (I/O) I: 0; O: 1 0
P3.7/UCA1RXD
(5)
/UCA1SOMI
(5)
7
UCA1RXD
(5)
/UCA1SOMI
(5)(2)
X 1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A/B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(4) If I
2
C functionality is selected, the output drives only the logical 0 to V
SS
level.
(5) MSP430F24x and MSP430F24x1 devices only
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