Datasheet

MSP430x241x, MSP430x261x
MIXED SIGNAL MICROCONTROLLER
SLAS541 -- JUNE 2007
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0x0FFFF to 0x0FFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0x0FFFE) contains 0x0FFFF (e.g. flash is not programmed) the CPU enters LPM4 after power-up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
Watchdog
Flash Key Violation
PC out of range (see Note 1)
PORIFG
WDTIFG
RSTIFG
KEYV (see Note 2)
Reset 0x0FFFE 31, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (see Notes 2 & 4)
(Non)maskable
(Non)maskable
(Non)maskable
0x0FFFC 30
Timer_B7 TBCCR0 CCIFG
(see Note 3)
Maskable 0x0FFFA 29
Timer_B7
TBCCR1 to TBCCR6
CCIFGs, TBIFG
(see Notes 2 & 3)
Maskable 0x0FFF8 28
Comparator_A+ CAIFG Maskable 0x0FFF6 27
Watchdog timer+ WDTIFG Maskable 0x0FFF4 26
Timer_A3 TACCR0 CCIFG (see Note 3) Maskable 0x0FFF2 25
Timer_A3 TACCR1 CCIFG
TACCR2 CCIFG
TAIFG(seeNote2&3)
Maskable 0x0FFF0 24
USCIA0/B0 Receive UCA0RXIFG, UCB0RXIFG
(see Note 2)
Maskable 0x0FFEE 23
USCIA0/B0 Transmit UCA0TXIFG, UCB0TXIFG
(see Note 2)
Maskable 0x0FFEC 22
ADC12 ADC12IFG (see Notes 2 & 3) Maskable 0x0FFEA 21
0x0FFE8 20
I/O port P2 (eight flags) P2IFG.0toP2IFG.7
(see Notes 2 & 3)
Maskable 0x0FFE6 19
I/O port P1 (eight flags)
P1IFG.0toP1IFG.7
(see Notes 2 & 3)
Maskable 0x0FFE4 18
USCIA1/B1 Receive UCA1RXIFG, UCB1RXIFG
(see Note 2)
Maskable 0x0FFE2 17
USCIA1/B1 Transmit UCA1TXIFG, UCB1TXIFG
(see Note 2)
Maskable 0x0FFE0 16
DMA DMA0IFG, DMA1IFG,
DMA2IFG (see Notes 2 & 3)
Maskable 0x0FFDE 15
DAC12 DAC12_0IFG, DAC12_1IFG
(see Notes 2 & 3)
Maskable 0x0FFDC 14
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NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range(0x00000 to 0x001FF)
or from within unused address ranges.
2. Multiple source flags.
3. Interrupt flags are located in the module.
4. Non-maskable: the individual interrupt-enable bit can disabl e an interrupt event, but the general-interrupt enable cannot.
5. The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY).
A 0x0AA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password i s supplied.
6. The interrupt vectors at addresses 0x0FFDA to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
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