Datasheet

MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF--0xFFC0. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External Reset
Watchdog
Flash key violation
PC out of range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset 0xFFFE 31, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 & 6)
(non)-maskable
(non)-maskable
(non)-maskable
0xFFFC 30
Timer_B3 TBCCR0 CCIFG (see Note 3) maskable 0xFFFA 29
Timer_B3
TBCCR1 and TBCCR2,
CCIFGs, TBIFG
(see Notes 2 & 3)
maskable 0xFFF8 28
Comparator_A+ CAIFG maskable 0xFFF6 27
Watchdog timer WDTIFG maskable 0xFFF4 26
Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0xFFF2 25
Timer_A3
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG (see Notes 2 & 3)
maskable 0xFFF0 24
USCI_A0/USCI_B0 Receive
USCI_B0 I2C Status
UCA0RXIFG, UCB0RXIFG
(see Note 2 and 4)
maskable 0xFFEE 23
USCI_A0/USCI_B0 Transmit
USCI_B0 I2C Receive / Transmit
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 5)
maskable 0xFFEC 22
0xFFEA 21
0xFFE8 20
I/O port P2 (eight flags) P2IFG.0toP2IFG.7
(see Notes 2 & 3)
maskable 0xFFE6 19
I/O port P1 (eight flags)
P1IFG.0toP1IFG.7
(see Notes 2 & 3)
maskable 0xFFE4 18
0xFFE2 17
0xFFE0 16
(see Note 7) 0xFFDE 15
(see Note 8) 0xFFDC--0xFFC0 14--0, lowest
NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000--0x01FF).
2. Multiple source flags.
3. Interrupt flags are located in the module.
4. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
5. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
6. Non-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
Non-maskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
7. This location is used as bootstrap loader security key (BSLSKEY).
A 0xAA55 at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.