Datasheet

Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
1
0
DVSS
DVCC
P1REN.x
To JTAG
From JTAG
1
Pad Logic
MSP430F22x2
MSP430F22x4
www.ti.com SLAS504G –JULY 2006–REVISED AUGUST 2012
Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access
Features
Table 22. Port P1 (P1.4 to P1.6) Pin Functions
CONTROL BITS/SIGNALS
(1)
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL.x 4-Wire JTAG
P1.4
(2)
(I/O) I: 0; O: 1 0 0
P1.4/SMCLK/TCK 4 SMCLK 1 1 0
TCK X X 1
P1.5
(2)
(I/O) I: 0; O: 1 0 0
P1.5/TA0/TMS 5 Timer_A3.TA0 1 1 0
TMS X X 1
P1.6
(2)
(I/O) I: 0; O: 1 0 0
P1.6/TA1/TDI/TCLK 6 Timer_A3.TA1 1 1 0
TDI/TCLK
(3)
X X 1
(1) X = Don't care
(2) Default after reset (PUC/POR)
(3) Function controlled by JTAG
Copyright © 2006–2012, Texas Instruments Incorporated 59