Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 38 16-Bit 16 MHz I/O number 32

MSP430F22x2

MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the

CPU goes into LPM4 immediately after power up.

Table 7. Interrupt Vector Addresses

SYSTEM

INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY

INTERRUPT

Power-up

PORIFG

External reset

RSTIFG

Watchdog Reset 0FFFEh 31, highest

WDTIFG

Flash key violation

KEYV

(2)

PC out-of-range

(1)

NMI NMIIFG (non)-maskable,

Oscillator fault OFIFG (non)-maskable, 0FFFCh 30

Flash memory access violation ACCVIFG

(2)(3)

(non)-maskable

Timer_B3 TBCCR0 CCIFG

(4)

maskable 0FFFAh 29

TBCCR1 and TBCCR2 CCIFGs,

Timer_B3 maskable 0FFF8h 28

TBIFG

(2)(4)

0FFF6h 27

Watchdog Timer WDTIFG maskable 0FFF4h 26

Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25

TACCR1 CCIFG

Timer_A3 TACCR2 CCIFG maskable 0FFF0h 24

TAIFG

(2)(4)

USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG

(2)

maskable 0FFEEh 23

USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG

(2)

maskable 0FFECh 22

ADC10 ADC10IFG

(4)

maskable 0FFEAh 21

0FFE8h 20

I/O Port P2

P2IFG.0 to P2IFG.7

(2)(4)

maskable 0FFE6h 19

(eight flags)

I/O Port P1

P1IFG.0 to P1IFG.7

(2)(4)

maskable 0FFE4h 18

(eight flags)

0FFE2h 17

0FFE0h 16

(5)

0FFDEh 15

(6)

0FFDCh to 0FFC0h 14 to 0, lowest

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address range.

(2) Multiple source flags

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

(4) Interrupt flags are located in the module.

(5) This location is used as bootstrap loader security key (BSLSKEY).

A 0AA55h at this location disables the BSL completely.

A zero (0h) disables the erasure of the flash if an invalid password is supplied.

(6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.