Datasheet

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  
SLAS439A − SEPTEMBER 2004 − REVISED JUNE 2005
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P2 pin schematic: P2.0 to P2.5, input/output with Schmitt-trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
1
0
DVSS
DVCC
P2REN.x
CAPD.x
Pad Logic
From Comparator_A
To Comparator_A
1
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/TA1/CA0
P2.4/TA2/CA1
P2.5/CA5
Control signal “From Comparator_A+”
PIN NAME
FUNCTION
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
FUNCTION
P2CA4 P2CA0 P2CA3 P2CA2 P2CA1
P2.0/ACLK/CA2
CA2 1 1 0 1 0
P2.1/INCLK/CA3
CA3 N/A N/A 0 1 1
P2.2/CAOUT/TA0/CA4
CA4 N/A N/A
OR
1 0 0
P2.3/TA1/CA0
CA0 0 1
OR
N/A N/A N/A
P2.4/TA2/CA1
CA1 1 0 0 0 1
P2.5/CA5
CA5 N/A N/A 1 0 1
NOTES: 1. N/A: Not available or not applicable.