Datasheet

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SLAS439A − SEPTEMBER 2004 − REVISED JUNE 2005
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f
TA
Timer_A clock frequency
Internal: SMCLK, ACLK;
External: TACLK, INCLK;
2.2 V 10
MHz
f
TA
Timer_A clock frequency
External: TACLK, INCLK;
Duty Cycle = 50% ±10%
3 V 16
MHz
t
TA,cap
Timer_A, capture timing TA0, TA1, TA2 2.2 V/3 V 20 ns
Comparator_A+ (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
(DD)
CAON=1, CARSEL=0, CAREF=0
2.2 V 25 40
µA
I
(DD)
CAON=1, CARSEL=0, CAREF=0
3 V 45 60
µ
A
I
(Refladder/RefDiode)
CAON=1, CARSEL=0,
CAREF=1/2/3, no load at
2.2 V 30 50
µA
I
(Refladder/RefDiode)
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
3 V 45 71
µ
A
V
(IC)
Common-mode input
voltage
CAON=1 2.2 V/3 V 0 V
CC
−1 V
V
(Ref025)
Voltage @ 0.25 V
CC
node
V
CC
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V 0.23 0.24 0.25
V
(Ref050)
Voltage @ 0.5V
CC
node
V
CC
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V 0.47 0.48 0.5
V
(RefVT)
(see Figure 19 and Figure 20)
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0/TA1 and
2.2 V 390 480 540
mV
V
(RefVT)
(see Figure 19 and Figure 20)
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, T
A
= 85°C
3 V 400 490 550
mV
V
(offset)
Offset voltage See Note 2 2.2 V/3 V −30 30 mV
V
hys
Input hysteresis CAON=1 2.2 V/3 V 0 0.7 1.4 mV
T
A
= 25°C, Overdrive 10 mV,
Without filter: CAF=0
2.2 V 80 165 300
ns
t
(response)
Response time
Without filter: CAF=0
(see Note 3, Figure 16 and
Figure 17)
3 V 70 120 240
ns
t
(response)
Response time
(low−high and high−low)
T
A
= 25°C, Overdrive 10 mV,
With filter: CAF=1
2.2 V 1.4 1.9 2.8
µs
With filter: CAF=1
(see Note 3, Figure 16 and
Figure 17)
3 V 0.9 1.5 2.2
µ
s
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to I
lkg(Px.x)
specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. Response time measured at P2.2/CAOUT.