Datasheet

Idle State
(Receiver
Enabled)
Receive
Disable
Receiver
Collects
Character
URXEx = 0
No Valid Start Bit
Not Completed
URXEx = 1
URXEx = 0
URXEx = 1
Valid Start Bit
Handle Interrupt
Conditions
Character
Received
URXEx = 1
URXEx = 0
USART Operation: UART Mode www.ti.com
Table 18-1. Receive Error Conditions
Error Condition Description
A framing error occurs when a low stop bit is detected. When two stop bits are used, only the first
Framing error
stop bit is checked for framing error. When a framing error is detected, the FE bit is set.
A parity error is a mismatch between the number of 1s in a character and the value of the parity
Parity error bit. When an address bit is included in the character, it is included in the parity calculation. When
a parity error is detected, the PE bit is set.
An overrun error occurs when a character is loaded into UxRXBUF before the prior character has
Receive overrun error
been read. When an overrun occurs, the OE bit is set.
A break condition is a period of 10 or more low bits received on URXDx after a missing stop bit.
Break condition When a break condition is detected, the BRK bit is set. A break condition can also set the
interrupt flag URXIFGx when URXEIE = 0.
When URXEIE = 0 and a framing error, parity error, or break condition is detected, no character is
received into UxRXBUF. When URXEIE = 1, characters are received into UxRXBUF and any applicable
error bit is set.
When any of the FE, PE, OE, BRK, or RXERR bits are set, the bit remains set until user software resets it
or UxRXBUF is read.
18.2.4 USART Receive Enable
The receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 18-5.
Disabling the USART receiver stops the receive operation following completion of any character currently
being received or immediately if no receive operation is active. The receive-data buffer, UxRXBUF,
contains the character moved from the RX shift register after the character is received.
Figure 18-5. State Diagram of Receiver Enable
NOTE: Re-Enabling the Receiver (Setting URXEx): UART Mode
When the receiver is disabled (URXEx = 0), re-enabling the receiver (URXEx = 1) is
asynchronous to any data stream that may be present on URXDx at the time.
Synchronization can be performed by testing for an idle line condition before receiving a valid
character (see URXWIE).
18.2.5 USART Transmit Enable
When UTXEx is set, the UART transmitter is enabled. Transmission is initiated by writing data to
UxTXBUF. The data is then moved to the transmit shift register on the next BITCLK after the TX shift
register is empty, and transmission begins. This process is shown in Figure 18-6.
When the UTXEx bit is reset the transmitter is stopped. Any data moved to UxTXBUF and any active
transmission of data currently in the transmit shift register prior to clearing UTXEx continue until all data
transmission is completed.
480
USART Peripheral Interface, UART Mode SLAU144J–December 2004–Revised July 2013
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated