Datasheet

Item n
PC.19:16
PC.15:0
SP
old
SP
0Program Counter Bits 19 to 1
19 15 1 016
www.ti.com CPU Registers
4.3 CPU Registers
The CPU incorporates 16 registers (R0 through R15). Registers R0, R1, R2, and R3 have dedicated
functions. Registers R4 through R15 are working registers for general use.
4.3.1 Program Counter (PC)
The 20-bit PC (PC/R0) points to the next instruction to be executed. Each instruction uses an even
number of bytes (2, 4, 6, or 8 bytes), and the PC is incremented accordingly. Instruction accesses are
performed on word boundaries, and the PC is aligned to even addresses. Figure 4-3 shows the PC.
Figure 4-3. Program Counter
The PC can be addressed with all instructions and addressing modes. A few examples:
MOV.W #LABEL,PC ; Branch to address LABEL (lower 64KB)
MOVA #LABEL,PC ; Branch to address LABEL (1MB memory)
MOV.W LABEL,PC ; Branch to address in word LABEL
; (lower 64KB)
MOV.W @R14,PC ; Branch indirect to address in
; R14 (lower 64KB)
ADDA #4,PC ; Skip two words (1MB memory)
The BR and CALL instructions reset the upper four PC bits to 0. Only addresses in the lower 64-KB
address range can be reached with the BR or CALL instruction. When branching or calling, addresses
beyond the lower 64-KB range can only be reached using the BRA or CALLA instructions. Also, any
instruction to directly modify the PC does so according to the used addressing mode. For example,
MOV.W #value,PC clears the upper four bits of the PC, because it is a .W instruction.
The PC is automatically stored on the stack with CALL (or CALLA) instructions and during an interrupt
service routine. Figure 4-4 shows the storage of the PC with the return address after a CALLA instruction.
A CALL instruction stores only bits 15:0 of the PC.
Figure 4-4. PC Storage on the Stack for CALLA
The RETA instruction restores bits 19:0 of the PC and adds 4 to the stack pointer (SP). The RET
instruction restores bits 15:0 to the PC and adds 2 to the SP.
4.3.2 Stack Pointer (SP)
The 20-bit SP (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts.
It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all
instructions and addressing modes. Figure 4-5 shows the SP. The SP is initialized into RAM by the user,
and is always aligned to even addresses.
119
SLAU144J–December 2004–Revised July 2013 CPUX
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