Datasheet

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17.4.12 IFG2, Interrupt Flag Register 2 ............................................................................. 472
17.4.13 UC1IE, USCI_B1 Interrupt Enable Register .............................................................. 472
17.4.14 UC1IFG, USCI_B1 Interrupt Flag Register ............................................................... 473
18 USART Peripheral Interface, UART Mode ............................................................................ 474
18.1 USART Introduction: UART Mode ..................................................................................... 475
18.2 USART Operation: UART Mode ....................................................................................... 476
18.2.1 USART Initialization and Reset .............................................................................. 476
18.2.2 Character Format .............................................................................................. 477
18.2.3 Asynchronous Communication Formats .................................................................... 477
18.2.4 USART Receive Enable ...................................................................................... 480
18.2.5 USART Transmit Enable ...................................................................................... 480
18.2.6 USART Baud Rate Generation .............................................................................. 481
18.2.7 USART Interrupts .............................................................................................. 487
18.3 USART Registers: UART Mode ........................................................................................ 490
18.3.1 UxCTL, USART Control Register ............................................................................ 491
18.3.2 UxTCTL, USART Transmit Control Register ............................................................... 492
18.3.3 UxRCTL, USART Receive Control Register ............................................................... 493
18.3.4 UxBR0, USART Baud Rate Control Register 0 ............................................................ 493
18.3.5 UxBR1, USART Baud Rate Control Register 1 ............................................................ 493
18.3.6 UxMCTL, USART Modulation Control Register ............................................................ 494
18.3.7 UxRXBUF, USART Receive Buffer Register ............................................................... 494
18.3.8 UxTXBUF, USART Transmit Buffer Register .............................................................. 494
18.3.9 IE1, Interrupt Enable Register 1 ............................................................................. 495
18.3.10 IE2, Interrupt Enable Register 2 ............................................................................ 495
18.3.11 IFG1, Interrupt Flag Register 1 ............................................................................. 495
18.3.12 IFG2, Interrupt Flag Register 2 ............................................................................. 496
19 USART Peripheral Interface, SPI Mode ............................................................................... 497
19.1 USART Introduction: SPI Mode ........................................................................................ 498
19.2 USART Operation: SPI Mode .......................................................................................... 499
19.2.1 USART Initialization and Reset .............................................................................. 499
19.2.2 Master Mode .................................................................................................... 500
19.2.3 Slave Mode ..................................................................................................... 500
19.2.4 SPI Enable ...................................................................................................... 501
19.2.5 Serial Clock Control ........................................................................................... 502
19.2.6 SPI Interrupts ................................................................................................... 504
19.3 USART Registers: SPI Mode ........................................................................................... 506
19.3.1 UxCTL, USART Control Register ............................................................................ 507
19.3.2 UxTCTL, USART Transmit Control Register ............................................................... 507
19.3.3 UxRCTL, USART Receive Control Register ............................................................... 508
19.3.4 UxBR0, USART Baud Rate Control Register 0 ............................................................ 508
19.3.5 UxBR1, USART Baud Rate Control Register 1 ............................................................ 508
19.3.6 UxMCTL, USART Modulation Control Register ............................................................ 508
19.3.7 UxRXBUF, USART Receive Buffer Register ............................................................... 508
19.3.8 UxTXBUF, USART Transmit Buffer Register .............................................................. 509
19.3.9 ME1, Module Enable Register 1 ............................................................................. 509
19.3.10 ME2, Module Enable Register 2 ............................................................................ 509
19.3.11 IE1, Interrupt Enable Register 1 ............................................................................ 509
19.3.12 IE2, Interrupt Enable Register 2 ............................................................................ 510
19.3.13 IFG1, Interrupt Flag Register 1 ............................................................................. 510
19.3.14 IFG2, Interrupt Flag Register 2 ............................................................................. 510
20 OA ................................................................................................................................. 511
20.1 OA Introduction ........................................................................................................... 512
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Contents SLAU144J–December 2004–Revised July 2013
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