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3.4.6.13 CLRZ
*CLRZ Clear zero bit
Syntax CLRZ
Operation 0 → Z
or
(.NOT.src .AND. dst → dst)
Emulation BIC #2,SR
Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination
operand. The result is placed into the destination. The clear zero bit instruction is a word
instruction.
Status Bits N: Not affected
Z: Reset to 0
C: Not affected
V: Not affected
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Example The zero bit in the status register is cleared.
CLRZ
76
CPU SLAU144J–December 2004–Revised July 2013
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