Datasheet

EEM Configurations

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28.3 EEM Configurations

Table 28-1 gives an overview of the EEM configurations in the MSP430 2xx family. The implemented

configuration is device dependent - see the device data sheet.

Table 28-1. 2xx EEM Configurations

Feature XS S M L

Memory Bus Triggers 2(=, ≠ only) 3 5 8

1) Low byte 1) Low byte 1) Low byte

Memory Bus Trigger Mask for All 16 or 20 bits

2) High byte 2) High byte 2) High byte

CPU Register-Write Triggers 0 1 1 2

Combination Triggers 2 4 6 8

Sequencer No No Yes Yes

State Storage No No No Yes

In general the following features can be found on any 2xx device:

• At least two MAB/MDB triggers supporting:

– Distinction between CPU, DMA, read, and write accesses

– =, ≠, ≥, or ≤ comparison (in XS only =, ≠)

• At least two trigger Combination registers

• Hardware breakpoints using the CPU Stop reaction

• Clock control with individual control of module clocks (in some XS configurations the control of module

clocks is hardwired)

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Embedded Emulation Module (EEM) SLAU144J–December 2004–Revised July 2013

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