Datasheet

SD24_A Registers www.ti.com
27.3.4 SD24MEMx, SD24_A Channel x Conversion Memory Register
15 14 13 12 11 10 9 8
Conversion Results
r r r r r r r r
7 6 5 4 3 2 1 0
Conversion Results
r r r r r r r r
Conversion Bits 15-0 Conversion results. The SD24MEMx register holds the upper or lower 16-bits of the digital filter output,
Results depending on the SD24LSBACC bit.
27.3.5 SD24PREx, SD24_A Channel x Preload Register
7 6 5 4 3 2 1 0
Preload Value
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
Preload Value Bits 7-0 SD24_A digital filter preload value
27.3.6 SD24AE, SD24_A Analog Input Enable Register
7 6 5 4 3 2 1 0
SD24AE7 SD24AE6 SD24AE5 SD24AE4 SD24AE3 SD24AE2 SD24AE1 SD24AE0
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
SD24AEx Bits 7-0 SD24_A analog enable
0 External input disabled. Negative inputs are internally connected to VSS.
1 External input enabled
636
SD24_A SLAU144J–December 2004–Revised July 2013
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