Datasheet

www.ti.com SD24_A Registers
SD24IFG Bit 2 SD24_A interrupt flag. SD24IFG is set when new conversion results are available. SD24IFG is automatically
reset when the corresponding SD24MEMx register is read, or may be cleared with software.
0 No interrupt pending
1 Interrupt pending
SD24SC Bit 1 SD24_A start conversion
0 No conversion start
1 Start conversion
SD24GRP Bit 0 SD24_A group. Groups SD24_A channel with next higher channel. Not used for the last channel.
0 Not grouped
1 Grouped
27.3.3 SD24INCTLx, SD24_A Channel x Input Control Register
7 6 5 4 3 2 1 0
SD24INTDLYx SD24GAINx SD24INCHx
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
SD24INTDLYx Bits 7-6 Interrupt delay generation after conversion start. These bits select the delay for the first interrupt after
conversion start.
00 Fourth sample causes interrupt
01 Third sample causes interrupt
10 Second sample causes interrupt
11 First sample causes interrupt
SD24GAINx Bits 5-3 SD24_A preamplifier gain
000 x1
001 x2
010 x4
011 x8
100 x16
101 x32
110 Reserved
111 Reserved
SD24INCHx Bits 2-0 SD24_A channel differential pair input. The available selections are device dependent. See the device-
specific data sheet.
000 Ax.0
001 Ax.1
(1)
010 Ax.2
(1)
011 Ax.3
(1)
100 Ax.4
(1)
101 (AV
CC
- AV
SS
) / 11
110 Temperature sensor
111 Short for PGA offset measurement
(1)
Ax.1 to Ax.4 not available on all devices (see device-specific data sheet).
635
SLAU144J–December 2004–Revised July 2013 SD24_A
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