Datasheet

SD24_A Registers www.ti.com
27.3.2 SD24CCTLx, SD24_A Channel x Control Register
15 14 13 12 11 10 9 8
Reserved SD24BUFx
(1)
SD24UNI SD24XOSR SD24SNGL SD24OSRx
r0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
7 6 5 4 3 2 1 0
SD24LSBTOG SD24LSBACC SD24OVIFG SD24DF SD24IE SD24IFG SD24SC SD24GRP
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r(w)-0
Reserved Bit 15 Reserved
SD24BUFx Bits 14-13 High-impedance input buffer mode
00 Buffer disabled
01 Slow speed/current
10 Medium speed/current
11 High speed/current
SD24UNI Bit 12 Unipolar mode select
0 Bipolar mode
1 Unipolar mode
SD24XOSR Bit 11 Extended oversampling ratio. This bit, along with the SD24OSRx bits, select the oversampling ratio. See
SD24OSRx bit description for settings.
SD24SNGL Bit 10 Single conversion mode select
0 Continuous conversion mode
1 Single conversion mode
SD24OSRx Bits 9-8 Oversampling ratio
When SD24XOSR = 0
00 256
01 128
10 64
11 32
When SD24XOSR = 1
00 512
01 1024
10 Reserved
11 Reserved
SD24LSBTOG Bit 7 LSB toggle. This bit, when set, causes SD24LSBACC to toggle each time the SD24MEMx register is read.
0 SD24LSBACC does not toggle with each SD24MEMx read
1 SD24LSBACC toggles with each SD24MEMx read
SD24LSBACC Bit 6 LSB access. This bit allows access to the upper or lower 16-bits of the SD24_A conversion result.
0 SD24MEMx contains the most significant 16-bits of the conversion.
1 SD24MEMx contains the least significant 16-bits of the conversion.
SD24OVIFG Bit 5 SD24_A overflow interrupt flag
0 No overflow interrupt pending
1 Overflow interrupt pending
SD24DF Bit 4 SD24_A data format
0 Offset binary
1 2s complement
SD24IE Bit 3 SD24_A interrupt enable
0 Disabled
1 Enabled
(1)
Not implemented on all devices (see the device-specific data sheet).Reserved with r0 access if high-impedance buffer not implemented.
634
SD24_A SLAU144J–December 2004–Revised July 2013
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