Datasheet

www.ti.com SD24_A Registers
27.3.1 SD24CTL, SD24_A Control Register
15 14 13 12 11 10 9 8
Reserved SD24XDIVx SD24LP
r0 r0 r0 r0 rw-0 rw-0 rw-0 rw-0
7 6 5 4 3 2 1 0
SD24DIVx SD24SSELx SD24VMIDON SD24REFON SD24OVIE Reserved
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r0
Reserved Bits 15-12 Reserved
SD24XDIVx Bits 11-9 SD24_A clock divider
00 /1
01 /3
10 /16
11 /48
1xx Reserved
SD24LP Bit 8 Low-power mode. This bit selects a reduced-speed reduced-power mode
0 Low-power mode is disabled
1 Low-power mode is enabled. The maximum clock frequency for the SD24_A is reduced.
SD24DIVx Bits 7-6 SD24_A clock divider
00 /1
01 /2
10 /4
11 /8
SD24SSELx Bits 5-4 SD24_A clock source select
00 MCLK
01 SMCLK
10 ACLK
11 External TACLK
SD24VMIDON Bit 3 VMID buffer on
0 Off
1 On
SD24REFON Bit 2 Reference generator on
0 Reference off
1 Reference on
SD24OVIE Bit 1 SD24_A overflow interrupt enable. The GIE bit must also be set to enable the interrupt.
0 Overflow interrupt disabled
1 Overflow interrupt enabled
Reserved Bit 0 Reserved
633
SLAU144J–December 2004–Revised July 2013 SD24_A
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