Datasheet

SD24_A Operation

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27.2.12 Interrupt Handling

The SD24_A has 2 interrupt sources for each ADC channel:

• SD24IFG

• SD24OVIFG

The SD24IFG bits are set when their corresponding SD24MEMx memory register is written with a

conversion result. An interrupt request is generated if the corresponding SD24IE bit and the GIE bit are

set. The SD24_A overflow condition occurs when a conversion result is written to any SD24MEMx location

before the previous conversion result was read.

27.2.12.1 SD24IV, Interrupt Vector Generator

All SD24_A interrupt sources are prioritized and combined to source a single interrupt vector. SD24IV is

used to determine which enabled SD24_A interrupt source requested an interrupt. The highest priority

SD24_A interrupt request that is enabled generates a number in the SD24IV register (see register

description). This number can be evaluated or added to the program counter to automatically enter the

appropriate software routine. Disabled SD24_A interrupts do not affect the SD24IV value.

Any access, read or write, of the SD24IV register has no effect on the SD24OVIFG or SD24IFG flags. The

SD24IFG flags are reset by reading the associated SD24MEMx register or by clearing the flags in

software. SD24OVIFG bits can only be reset with software.

If another interrupt is pending after servicing of an interrupt, another interrupt is generated. For example, if

the SD24OVIFG and one or more SD24IFG interrupts are pending when the interrupt service routine

accesses the SD24IV register, the SD24OVIFG interrupt condition is serviced first and the corresponding

flag(s) must be cleared in software. After the RETI instruction of the interrupt service routine is executed,

the highest priority SD24IFG pending generates another interrupt request.

27.2.12.2 Interrupt Delay Operation

The SD24INTDLYx bits control the timing for the first interrupt service request for the corresponding

channel. This feature delays the interrupt request for a completed conversion by up to four conversion

cycles allowing the digital filter to settle prior to generating an interrupt request. The delay is applied each

time the SD24SC bit is set or when the SD24GAINx or SD24INCHx bits for the channel are modified.

SD24INTDLYx disables overflow interrupt generation for the channel for the selected number of delay

cycles. Interrupt requests for the delayed conversions are not generated during the delay.

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SD24_A SLAU144J–December 2004–Revised July 2013

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