Datasheet

Input
Voltage
SD24MEMx
−V
FSR
+V
FSR
7FFFh
8000h
Bipolar Output: 2’s complement
Input
Voltage
SD24MEMx
−V
FSR
+V
FSR
FFFFh
8000h
Bipolar Output: Offset Binary
0000h
0000h
SD24MEMx
−V
FSR
FFFFh
Unipolar Output
Input
Voltage
+V
FSR
0000h
www.ti.com SD24_A Operation
27.2.8 Conversion Memory Register: SD24MEMx
One SD24MEMx register is associated with each SD24_A channel. Conversion results are moved to the
corresponding SD24MEMx register with each decimation step of the digital filter. The SD24IFG bit is set
when new data is written to SD24MEMx. SD24IFG is automatically cleared when SD24MEMx is read by
the CPU or may be cleared with software.
27.2.8.1 Output Data Format
The output data format is configurable in twos complement, offset binary or unipolar mode as shown in
Table 27-3. The data format is selected by the SD24DF and SD24UNI bits.
Table 27-3. Data Format
Digital Filter Output
SD24UNI SD24DF Format Analog Input SD24MEMx
(1)
(OSR = 256)
+FSR FFFF FFFFFF
0 0 Bipolar offset binary ZERO 8000 800000
-FSR 0000 000000
+FSR 7FFF 7FFFFF
0 1 Bipolar twos compliment ZERO 0000 000000
-FSR 8000 800000
+FSR FFFF FFFFFF
1 0 Unipolar ZERO 0000 800000
-FSR 0000 000000
(1)
Independent of SD24OSRx and SD24XOSR settings; SD24LSBACC = 0.
NOTE: Offset Measurements and Data Format
Any offset measurement done either externally or using the internal differential pair A7 would
be appropriate only when the channel is operating under bipolar mode with SD24UNI = 0.
If the measured value is to be used in the unipolar mode for offset correction it needs to be
multiplied by two.
Figure 27-6 shows the relationship between the full-scale input voltage range from -V
FSR
to +V
FSR
and the
conversion result. The data formats are illustrated.
Figure 27-6. Input Voltage vs Digital Output
625
SLAU144J–December 2004–Revised July 2013 SD24_A
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