Datasheet
048121620
24
15 3 269 723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=512, LSBACC=0, SD24UNI=0
048121620
24
15 3 269 723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=512, LSBACC=1, SD24UNI=0
048121620
24
15 3 269 723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=512, LSBACC=0, SD24UNI=1
048121620
24
15 3 269 723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=512, LSBACC=1, SD24UNI=1
048121620
24
15 3 269 723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=1024, LSBACC=0, SD24UNI=0
048121620
24
15 3 269 723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=1024, LSBACC=1, SD24UNI=0
04812162024 15 3 269 723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=1024, LSBACC=0, SD24UNI=1
048121620
24
15 3 269 723 22 21 19 18 17 15 14 13 11 1028 27 26 2529
OSR=1024, LSBACC=1, SD24UNI=1
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SD24_A Operation
27.2.7.1 Digital Filter Output
The number of bits output by the digital filter is dependent on the oversampling ratio and ranges from 15
to 30 bits. Figure 27-5 shows the digital filter output and their relation to SD24MEMx for each OSR,
LSBACC, and SD24UNI setting. For example, for OSR = 1024, LSBACC = 0, and SD24UNI = 1, the
SD24MEMx register contains bits 28 to 13 of the digital filter output. When OSR = 32, the one (SD24UNI
= 0) or two (SD24UNI = 1) LSBs are always zero.
The SD24LSBACC and SD24LSBTOG bits give access to the least significant bits of the digital filter
output. When SD24LSBACC = 1 the 16 least significant bits of the digital filter's output are read from
SD24MEMx using word instructions. The SD24MEMx register can also be accessed with byte instructions
returning only the 8 least significant bits of the digital filter output.
When SD24LSBTOG = 1 the SD24LSBACC bit is automatically toggled each time SD24MEMx is read.
This allows the complete digital filter output result to be read with two reads of SD24MEMx. Setting or
clearing SD24LSBTOG does not change SD24LSBACC until the next SD24MEMx access.
623
SLAU144J–December 2004–Revised July 2013 SD24_A
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