Datasheet

3 3
M M
M M
f f
sinc OSR × × sin OSR × ×
f f
1
H(f) = = ×
OSR
f f
sinc × sin ×
f f
p p
p p
é ù é ù
æ ö æ ö
ê ú ê ú
ç ÷ ç ÷
ç ÷ ç ÷
ê ú ê ú
è ø è ø
ê ú ê ú
æ ö æ ö
ê ú ê ú
ç ÷ ç ÷
ç ÷ ç ÷
ê ú ê ú
è ø è ø
ë û ë û
3
-OSR
-1
1 1 – z
H(z) = ×
OSR
1 – z
æ ö
ç ÷
ç ÷
è ø
CC CC
M Ax S+ S–
Settling
AV AV
1
f = and V = max – V , – V
2 × t 2 2
æ ö
ç ÷
ç ÷
è ø
17
Ax
Settling S S
REF
GAIN × 2 × V
t (R + 1 k ) × C × ln
V
æ ö
ç ÷
³ W
ç ÷
è ø
www.ti.com SD24_A Operation
When the buffers are used, R
S
does not affect the sampling frequency f
S
. However, when the buffers are
not used or are not present on the device, the maximum modulator frequency f
M
may be calculated from
the minimum settling time t
Settling
of the sampling circuit given by:
Where,
with V
S+
and V
S-
referenced to AV
SS
.
C
S
varies with the gain setting as shown in Table 27-2.
Table 27-2. Sampling Capacitance
PGA Gain Sampling Capacitance (C
S
)
1 1.25 pF
2, 4 2.5 pF
8 5 pF
16, 32 10 pF
27.2.7 Digital Filter
The digital filter processes the 1-bit data stream from the modulator using a SINC
3
comb filter. The
transfer function is described in the z-Domain by:
and in the frequency domain by:
where the oversampling rate, OSR, is the ratio of the modulator frequency f
M
to the sample frequency f
S
.
Figure 27-3 shows the filter's frequency response for an OSR of 32. The first filter notch is at f
S
= f
M
/OSR.
The notch frequency can be adjusted by changing the modulator frequency, f
M
, using SD24SSELx and
SD24DIVx and the oversampling rate using the SD24OSRx and SD24XOSR bits.
The digital filter for each enabled ADC channel completes the decimation of the digital bit-stream and
outputs new conversion results to the corresponding SD24MEMx register at the sample frequency f
S
.
621
SLAU144J–December 2004–Revised July 2013 SD24_A
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