Datasheet

0xxx
4xxx
8xxx
Cxxx
1xxx
14xx
18xx
1Cxx
20xx
24xx
28xx
2Cxx
30xx
34xx
38xx
3Cxx
4xxx
5xxx
6xxx
7xxx
8xxx
9xxx
Axxx
Bxxx
Cxxx
Dxxx
Exxx
Fxxx
RRC
RRC.B
SWPB RRA RRA.B SXT PUSH PUSH.B CALL RETI
000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340
380 3C0
JNE/JNZ
JEQ/JZ
JNC
JC
JN
JGE
JL
JMP
MOV, MOV.B
ADD, ADD.B
ADDC, ADDC.B
SUBC, SUBC.B
SUB, SUB.B
CMP, CMP.B
DADD, DADD.B
BIT, BIT.B
BIC, BIC.B
BIS, BIS.B
XOR, XOR.B
AND, AND.B
Instruction Set www.ti.com
3.4.5 Instruction Set Description
The instruction map is shown in Figure 3-12 and the complete instruction set is summarized in Table 3-17.
Figure 3-12. Core Instruction Map
Table 3-17. MSP430 Instruction Set
Mnemonic Description V N Z C
ADC(.B)
(1)
dst
Add C to destination dst + C → dst * * * *
ADD(.B) src,dst
Add source to destination src + dst → dst * * * *
ADDC(.B) src,dst
Add source and C to destination src + dst + C → dst * * * *
AND(.B) src,dst
AND source and destination src .and. dst → dst 0 * * *
BIC(.B) src,dst
Clear bits in destination not.src .and. dst → dst - - - -
BIS(.B) src,dst
Set bits in destination src .or. dst → dst - - - -
BIT(.B) src,dst
Test bits in destination src .and. dst 0 * * *
BR
(1)
dst
Branch to destination dst → PC - - - -
CALL dst
Call destination PC+2 → stack, dst → PC - - - -
CLR(.B)
(1)
dst
Clear destination 0 → dst - - - -
CLRC
(1)
Clear C 0 → C - - - 0
CLRN
(1)
Clear N 0 → N - 0 - -
CLRZ
(1)
Clear Z 0 → Z - - 0 -
CMP(.B) src,dst
Compare source and destination dst - src * * * *
DADC(.B)
(1)
dst
Add C decimally to destination dst + C → dst (decimally) * * * *
DADD(.B) src,dst
Add source and C decimally to dst src + dst + C → dst (decimally) * * * *
DEC(.B)
(1)
dst
Decrement destination dst - 1 → dst * * * *
(1)
Emulated Instruction
62
CPU SLAU144J–December 2004–Revised July 2013
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