Datasheet

FSR
1.2 V
2
±V = = ±0.6 V
1
REF
FSR
PGA
V
2
V =
GAIN
www.ti.com SD24_A Operation
27.2 SD24_A Operation
The SD24_A module is configured with user software. The setup and operation of the SD24_A is
discussed in the following sections.
27.2.1 ADC Core
The analog-to-digital conversion is performed by a 1-bit second-order sigma-delta modulator. A single-bit
comparator within the modulator quantizes the input signal with the modulator frequency f
M
. The resulting
1-bit data stream is averaged by the digital filter for the conversion result.
27.2.2 Analog Input Range and PGA
The full-scale input voltage range for each analog input pair is dependent on the gain setting of the
programmable gain amplifier of each channel. The maximum full-scale range is ±V
FSR
where V
FSR
is
defined by:
For a 1.2-V reference, the maximum full-scale input range for a gain of 1 is:
See the device-specific data sheet for full-scale input specifications.
27.2.3 Voltage Reference Generator
The SD24_A module has a built-in 1.2-V reference. It can be used for each SD24_A channel and is
enabled by the SD24REFON bit. When using the internal reference an external 100-nF capacitor
connected from V
REF
to AV
SS
is recommended to reduce noise. The internal reference voltage can be used
off-chip when SD24VMIDON = 1. The buffered output can provide up to 1 mA of drive. When using the
internal reference off-chip, a 470-nF capacitor connected from V
REF
to AV
SS
is required. See device-
specific data sheet for parameters.
An external voltage reference can be applied to the V
REF
input when SD24REFON and SD24VMIDON are
both reset.
27.2.4 Auto Power-Down
The SD24_A is designed for low-power applications. When the SD24_A is not actively converting, it is
automatically disabled and automatically re-enabled when a conversion is started. The reference is not
automatically disabled, but it can be disabled by setting SD24REFON = 0. When the SD24_A or reference
are disabled, they consume no current.
27.2.5 Analog Input Pair Selection
The SD24_A can convert up to eight differential input pairs multiplexed into the PGA. Up to five analog
input pairs (A0 to A4) are available externally on the device. A resistive divider to measure the supply
voltage is available using the A5 multiplexer input. An internal temperature sensor is available using the
A6 multiplexer input.
Input A7 is a shorted connection between the + and – input pair and can be used to calibrate the offset of
the SD24_A input stage. Note that the measured offset depends on the impedance of the external
circuitry; thus, the actual offset seen at any of the analog inputs may be different.
27.2.5.1 Analog Input Setup
The analog input of each channel is configured using the SD24INCTLx register. These settings can be
independently configured for each SD24_A channel.
619
SLAU144J–December 2004–Revised July 2013 SD24_A
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