Datasheet

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SD16_A Registers
26.3.2 SD16CCTL0, SD16_A Control Register 0
15 14 13 12 11 10 9 8
Reserved SD16BUFx
(1)
SD16UNI SD16XOSR SD16SNGL SD16OSRx
r0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
7 6 5 4 3 2 1 0
SD16LSBTOG SD16LSBACC SD16OVIFG SD16DF SD16IE SD16IFG SD16SC Reserved
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-0
Reserved Bit 15 Reserved
SD16BUFx Bits 14-13 High-impedance input buffer mode
00 Buffer disabled
01 Slow speed/current
10 Medium speed/current
11 High speed/current
SD16UNI Bit 12 Unipolar mode select
0 Bipolar mode
1 Unipolar mode
SD16XOSR Bit 11 Extended oversampling ratio. This bit, along with the SD16OSRx bits, select the oversampling ratio. See
SD16OSRx bit description for settings.
SD16SNGL Bit 10 Single conversion mode select
0 Continuous conversion mode
1 Single conversion mode
SD16OSRx Bits 9-8 Oversampling ratio
When SD16XOSR = 0
00 256
01 128
10 64
11 32
When SD16XOSR = 1
00 512
01 1024
10 Reserved
11 Reserved
SD16LSBTOG Bit 7 LSB toggle. This bit, when set, causes SD16LSBACC to toggle each time the SD16MEM0 register is read.
0 SD16LSBACC does not toggle with each SD16MEM0 read
1 SD16LSBACC toggles with each SD16MEM0 read
SD16LSBACC Bit 6 LSB access. This bit allows access to the upper or lower 16-bits of the SD16_A conversion result.
0 SD16MEMx contains the most significant 16-bits of the conversion.
1 SD16MEMx contains the least significant 16-bits of the conversion.
SD16OVIFG Bit 5 SD16_A overflow interrupt flag
0 No overflow interrupt pending
1 Overflow interrupt pending
SD16DF Bit 4 SD16_A data format
0 Offset binary
1 2's complement
SD16IE Bit 3 SD16_A interrupt enable
0 Disabled
1 Enabled
SD16IFG Bit 2 SD16_A interrupt flag. SD16IFG is set when new conversion results are available. SD16IFG is automatically
reset when the corresponding SD16MEMx register is read, or may be cleared with software.
0 No interrupt pending
1 Interrupt pending
(1)
Reserved in MSP430x20x3 devices
613
SLAU144JDecember 2004Revised July 2013 SD16_A
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